/* * board.c * * Board functions for TI AM43XX based boards * * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include #include "board.h" #include #include DECLARE_GLOBAL_DATA_PTR; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* * Read header information from EEPROM into global structure. */ static int read_eeprom(struct am43xx_board_id *header) { /* Check if baseboard eeprom is available */ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { printf("Could not probe the EEPROM at 0x%x\n", CONFIG_SYS_I2C_EEPROM_ADDR); return -ENODEV; } /* read the eeprom using i2c */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, sizeof(struct am43xx_board_id))) { printf("Could not read the EEPROM\n"); return -EIO; } if (header->magic != 0xEE3355AA) { /* * read the eeprom using i2c again, * but use only a 1 byte address */ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, sizeof(struct am43xx_board_id))) { printf("Could not read the EEPROM at 0x%x\n", CONFIG_SYS_I2C_EEPROM_ADDR); return -EIO; } if (header->magic != 0xEE3355AA) { printf("Incorrect magic number (0x%x) in EEPROM\n", header->magic); return -EINVAL; } } strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); am43xx_board_name[sizeof(header->name)] = 0; return 0; } #ifdef CONFIG_SPL_BUILD #define NUM_OPPS 6 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { { /* 19.2 MHz */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ }, { /* 24 MHz */ {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 25 MHz */ {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ }, { /* 26 MHz */ {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ }, }; const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ }; const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ }; const struct dpll_params epos_evm_dpll_ddr = { 266, 24, 1, -1, 1, -1, -1}; const struct dpll_params gp_evm_dpll_ddr = { 400, 23, 1, -1, 1, -1, -1}; const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, .emif_sdram_config_ext = 0x1, }; const struct emif_regs emif_regs_lpddr2 = { .sdram_config = 0x808012BA, .ref_ctrl = 0x0000040D, .sdram_tim1 = 0xEA86B411, .sdram_tim2 = 0x103A094A, .sdram_tim3 = 0x0F6BA37F, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E084006, .emif_rd_wr_exec_thresh = 0x00000405, .emif_ddr_ext_phy_ctrl_1 = 0x04010040, .emif_ddr_ext_phy_ctrl_2 = 0x00500050, .emif_ddr_ext_phy_ctrl_3 = 0x00500050, .emif_ddr_ext_phy_ctrl_4 = 0x00500050, .emif_ddr_ext_phy_ctrl_5 = 0x00500050 }; const u32 ext_phy_ctrl_const_base_lpddr2[] = { 0x00500050, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00350035, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40001000, 0x08102040 }; const struct ctrl_ioregs ioregs_ddr3 = { .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, .emif_sdram_config_ext = 0x0143, }; const struct emif_regs ddr3_emif_regs_400Mhz = { .sdram_config = 0x638413B2, .ref_ctrl = 0x00000C30, .sdram_tim1 = 0xEAAAD4DB, .sdram_tim2 = 0x266B7FDA, .sdram_tim3 = 0x107F8678, .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, .emif_ddr_phy_ctlr_1 = 0x0E004008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00400040, .emif_ddr_ext_phy_ctrl_3 = 0x00400040, .emif_ddr_ext_phy_ctrl_4 = 0x00400040, .emif_ddr_ext_phy_ctrl_5 = 0x00400040, .emif_rd_wr_lvl_rmp_win = 0x0, .emif_rd_wr_lvl_rmp_ctl = 0x0, .emif_rd_wr_lvl_ctl = 0x0, .emif_rd_wr_exec_thresh = 0x00000405 }; const 
/*
    ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/**
 * @file ch.h
 * @brief ChibiOS/RT main include file, it includes everything else.
 * @addtogroup kernel_info
 * @{
 */

#ifndef _CH_H_
#define _CH_H_

/**
 * ChibiOS/RT identification macro.
 */
#define _CHIBIOS_RT_

/**
 * Kernel version string.
 */
#define CH_KERNEL_VERSION       "1.3.3unstable"

/**
 * Kernel version major number.
 */
#define CH_KERNEL_MAJOR         1

/**
 * Kernel version minor number.
 */
#define CH_KERNEL_MINOR         3

/**
 * Kernel version patch number.
 */
#define CH_KERNEL_PATCH         3

/*
 * Common values.
 */
#ifndef FALSE
#define FALSE       0
#endif
#ifndef TRUE
#define TRUE        (!FALSE)
#endif

#include <chconf.h>
#include <chtypes.h>
#include "lists.h"
#include <chcore.h>
#include "sys.h"
#include "vt.h"
#include "scheduler.h"
#include "semaphores.h"
#include "mutexes.h"
#include "condvars.h"
#include "events.h"
#include "messages.h"
#include "mailboxes.h"
#include "memcore.h"
#include "heap.h"
#include "mempools.h"
#include "threads.h"
#include "inline.h"
#include "queues.h"
#include "channels.h"
#include "debug.h"

#endif /* _CH_H_ */

/** @} */
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