/****************************************************************************** * serial.c * * Framework for serial device drivers. * * Copyright (c) 2003-2005, K A Fraser */ #include #include #include #include #include #include #include static struct serial_port com[2] = { { .lock = SPIN_LOCK_UNLOCKED }, { .lock = SPIN_LOCK_UNLOCKED } }; void serial_rx_interrupt(struct serial_port *port, struct cpu_user_regs *regs) { char c; serial_rx_fn fn = NULL; unsigned long flags; spin_lock_irqsave(&port->lock, flags); if ( port->driver->getc(port, &c) ) { if ( port->rx != NULL ) fn = port->rx; else if ( (c & 0x80) && (port->rx_hi != NULL) ) fn = port->rx_hi; else if ( !(c & 0x80) && (port->rx_lo != NULL) ) fn = port->rx_lo; else if ( (port->rxbufp - port->rxbufc) != SERIAL_RXBUFSZ ) port->rxbuf[MASK_SERIAL_RXBUF_IDX(port->rxbufp++)] = c; } spin_unlock_irqrestore(&port->lock, flags); if ( fn != NULL ) (*fn)(c & 0x7f, regs); } void serial_tx_interrupt(struct serial_port *port, struct cpu_user_regs *regs) { int i; unsigned long flags; spin_lock_irqsave(&port->lock, flags); if ( port->driver->tx_empty(port) ) { for ( i = 0; i < port->tx_fifo_size; i++ ) { if ( port->txbufc == port->txbufp ) break; port->driver->putc( port, port->txbuf[MASK_SERIAL_TXBUF_IDX(port->txbufc++)]); } } spin_unlock_irqrestore(&port->lock, flags); } static void __serial_putc(struct serial_port *port, char c) { int i; if ( (port->txbuf != NULL) && !port->sync ) { /* Interrupt-driven (asynchronous) transmitter. */ if ( (port->txbufp - port->txbufc) == SERIAL_TXBUFSZ ) { /* Buffer is full: we spin, but could alternatively drop chars. */ while ( !port->driver->tx_empty(port) ) cpu_relax(); for ( i = 0; i < port->tx_fifo_size; i++ ) port->driver->putc( port, port->txbuf[MASK_SERIAL_TXBUF_IDX(port->txbufc++)]); port->txbuf[MASK_SERIAL_TXBUF_IDX(port->txbufp++)] = c; } else if ( ((port->txbufp - port->txbufc) == 0) && port->driver->tx_empty(port) ) { /* Buffer and UART FIFO are both empty. */ port->driver->putc(port, c); } else { /* Normal case: buffer the character. */ port->txbuf[MASK_SERIAL_TXBUF_IDX(port->txbufp++)] = c; } } else if ( port->driver->tx_empty ) { /* Synchronous finite-capacity transmitter. */ while ( !port->driver->tx_empty(port) ) cpu_relax(); port->driver->putc(port, c); } else { /* Simple synchronous transmitter. */ port->driver->putc(port, c); } } void serial_putc(int handle, char c) { struct serial_port *port = &com[handle & SERHND_IDX]; unsigned long flags; if ( (handle == -1) || !port->driver || !port->driver->putc ) return; spin_lock_irqsave(&port->lock, flags); if ( (c == '\n') && (handle & SERHND_COOKED) ) __serial_putc(port, '\r'); if ( handle & SERHND_HI ) c |= 0x80; else if ( handle & SERHND_LO ) c &= 0x7f; __serial_putc(port, c); spin_unlock_irqrestore(&port->lock, flags); } void serial_puts(int handle, const char *s) { struct serial_port *port = &com[handle & SERHND_IDX]; unsigned long flags; char c; if ( (handle == -1) || !port->driver || !port->driver->putc ) return; spin_lock_irqsave(&port->lock, flags); while ( (c = *s++) != '\0' ) { if ( (c == '\n') && (handle & SERHND_COOKED) ) __serial_putc(port, '\r'); if ( handle & SERHND_HI ) c |= 0x80; else if ( handle & SERHND_LO ) c &= 0x7f; __serial_putc(port, c); } spin_unlock_irqrestore(&port->lock, flags); } char serial_getc(int handle) { struct serial_port *port = &com[handle & SERHND_IDX]; char c; unsigned long flags; if ( (handle == -1) || !port->driver || !port->driver->getc ) return '\0'; do { for ( ; ; ) { spin_lock_irqsave(&port->lock, flags); if ( port->rxbufp != port->rxbufc ) { c = port->rxbuf[MASK_SERIAL_RXBUF_IDX(port->rxbufc++)]; spin_unlock_irqrestore(&port->lock, flags); break; } if ( port->driver->getc(port, &c) ) { spin_unlock_irqrestore(&port->lock, flags); break; } spin_unlock_irqrestore(&port->lock, flags); cpu_relax(); } } while ( ((handle & SERHND_LO) && (c & 0x80)) || ((handle & SERHND_HI) && !(c & 0x80)) ); return c & 0x7f; } int serial_parse_handle(char *conf) { int handle; /* Silently fail if user has explicitly requested no serial I/O. */ if ( strcmp(conf, "none") == 0 ) return -1; if ( strncmp(conf, "com", 3) != 0 ) goto fail; switch ( conf[3] ) { case '1': handle = 0; break; case '2': handle = 1; break; default: goto fail; } if ( conf[4] == 'H' ) handle |= SERHND_HI; else if ( conf[4] == 'L' ) handle |= SERHND_LO; handle |= SERHND_COOKED; return handle; fail: printk("ERROR: bad serial-interface specification '%s'\n", conf); return -1; } void serial_set_rx_handler(int handle, serial_rx_fn fn) { struct serial_port *port = &com[handle & SERHND_IDX]; unsigned long flags; if ( handle == -1 ) return; spin_lock_irqsave(&port->lock, flags); if ( port->rx != NULL ) goto fail; if ( handle & SERHND_LO ) { if ( port->rx_lo != NULL ) goto fail; port->rx_lo = fn; } else if ( handle & SERHND_HI ) { if ( port->rx_hi != NULL ) goto fail; port->rx_hi = fn; } else { if ( (port->rx_hi != NULL) || (port->rx_lo != NULL) ) goto fail; port->rx = fn; } spin_unlock_irqrestore(&port->lock, flags); return; fail: spin_unlock_irqrestore(&port->lock, flags); printk("ERROR: Conflicting receive handlers for COM%d\n", handle & SERHND_IDX); } void serial_force_unlock(int handle) { struct serial_port *port = &com[handle & SERHND_IDX]; if ( handle != -1 ) port->lock = SPIN_LOCK_UNLOCKED; serial_start_sync(handle); } void serial_start_sync(int handle) { struct serial_port *port = &com[handle & SERHND_IDX]; unsigned long flags; if ( handle == -1 ) return; spin_lock_irqsave(&port->lock, flags); if ( port->sync++ == 0 ) { while ( (port->txbufp - port->txbufc) != 0 ) { while ( !port->driver->tx_empty(port) ) cpu_relax(); port->driver->putc( port, port->txbuf[MASK_SERIAL_TXBUF_IDX(port->txbufc++)]); } } spin_unlock_irqrestore(&port->lock, flags); } void serial_end_sync(int handle) { struct serial_port *port = &com[handle & SERHND_IDX]; unsigned long flags; if ( handle == -1 ) return; spin_lock_irqsave(&port->lock, flags); port->sync--; spin_unlock_irqrestore(&port->lock, flags); } int serial_tx_space(int handle) { struct serial_port *port = &com[handle & SERHND_IDX]; if ( handle == -1 ) return SERIAL_TXBUFSZ; return SERIAL_TXBUFSZ - (port->txbufp - port->txbufc); } void serial_init_preirq(void) { int i; for ( i = 0; i < ARRAY_SIZE(com); i++ ) if ( com[i].driver && com[i].driver->init_preirq ) com[i].driver->init_preirq(&com[i]); } void serial_init_postirq(void) { int i; for ( i = 0; i < ARRAY_SIZE(com); i++ ) if ( com[i].driver && com[i].driver->init_postirq ) com[i].driver->init_postirq(&com[i]); } void serial_endboot(void) { int i; for ( i = 0; i < ARRAY_SIZE(com); i++ ) if ( com[i].driver && com[i].driver->endboot ) com[i].driver->endboot(&com[i]); } void serial_register_uart(int idx, struct uart_driver *driver, void *uart) { /* Store UART-specific info. */ com[idx].driver = driver; com[idx].uart = uart; /* Default is no transmit FIFO. */ com[idx].tx_fifo_size = 1; } void serial_async_transmit(struct serial_port *port) { BUG_ON(!port->driver->tx_empty); if ( port->txbuf == NULL ) port->txbuf = alloc_xenheap_pages( get_order_from_bytes(SERIAL_TXBUFSZ)); } /* * Local variables: * mode: C * c-set-style: "BSD" * c-basic-offset: 4 * tab-width: 4 * indent-tabs-mode: nil * End: */ 5 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 
/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/**
 * @file    STM32F1xx/stm32_dma.c
 * @brief   DMA helper driver code.
 *
 * @addtogroup STM32F1xx_DMA
 * @details DMA sharing helper driver. In the STM32 the DMA streams are a
 *          shared resource, this driver allows to allocate and free DMA
 *          streams at runtime in order to allow all the other device
 *          drivers to coordinate the access to the resource.
 * @note    The DMA ISR handlers are all declared into this module because
 *          sharing, the various device drivers can associate a callback to
 *          IRSs when allocating streams.
 * @{
 */

#include "ch.h"
#include "hal.h"

/* The following macro is only defined if some driver requiring DMA services
   has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)

/*===========================================================================*/
/* Driver local definitions.                                                 */
/*===========================================================================*/

/**
 * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
 */
#define STM32_DMA1_STREAMS_MASK     0x0000007F

/**
 * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
 */
#define STM32_DMA2_STREAMS_MASK     0x00000F80

/**
 * @brief   Post-reset value of the stream CCR register.
 */
#define STM32_DMA_CCR_RESET_VALUE   0x00000000

/*===========================================================================*/
/* Driver exported variables.                                                */
/*===========================================================================*/

/**
 * @brief   DMA streams descriptors.
 * @details This table keeps the association between an unique stream
 *          identifier and the involved physical registers.
 * @note    Don't use this array directly, use the appropriate wrapper macros
 *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
 */
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
#else /* !STM32F10X_CL */
  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn},
  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn},
#endif /* !STM32F10X_CL */
#endif /* STM32_HAS_DMA2 */
};

/*===========================================================================*/
/* Driver local variables and types.                                         */
/*===========================================================================*/

/**
 * @brief   DMA ISR redirector type.
 */
typedef struct {
  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
  void                  *dma_param;     /**< @brief DMA callback parameter. */
} dma_isr_redir_t;

/**
 * @brief   Mask of the allocated streams.
 */
static uint32_t dma_streams_mask;

/**
 * @brief   DMA IRQ redirectors.
 */
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];

/*===========================================================================*/
/* Driver local functions.                                                   */
/*===========================================================================*/

/*===========================================================================*/
/* Driver interrupt handlers.                                                */
/*===========================================================================*/

/**
 * @brief   DMA1 stream 1 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
  if (dma_isr_redir[0].dma_func)
    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 2 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
  if (dma_isr_redir[1].dma_func)
    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 3 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
  if (dma_isr_redir[2].dma_func)
    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 4 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
  if (dma_isr_redir[3].dma_func)
    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 5 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
  if (dma_isr_redir[4].dma_func)
    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 6 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;
  if (dma_isr_redir[5].dma_func)
    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA1 stream 7 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;
  if (dma_isr_redir[6].dma_func)
    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
/**
 * @brief   DMA2 stream 1 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;
  if (dma_isr_redir[7].dma_func)
    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA2 stream 2 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;
  if (dma_isr_redir[8].dma_func)
    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA2 stream 3 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;
  if (dma_isr_redir[9].dma_func)
    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
/**
 * @brief   DMA2 stream 4 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
  if (dma_isr_redir[10].dma_func)
    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

  CH_IRQ_EPILOGUE();
}

/**
 * @brief   DMA2 stream 5 shared interrupt handler.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
  if (dma_isr_redir[11].dma_func)
    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

  CH_IRQ_EPILOGUE();
}
#else /* !STM32F10X_CL */
/**
 * @brief   DMA2 streams 4 and 5 shared interrupt handler.
 * @note    This IRQ is shared between DMA2 channels 4 and 5 so it is a
 *          bit less efficient because an extra check.
 *
 * @isr
 */
CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
  uint32_t flags;

  CH_IRQ_PROLOGUE();

  /* Check on channel 4.*/
  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
  if (flags & STM32_DMA_ISR_MASK) {
    DMA2->IFCR = STM32_DMA_ISR_MASK << 12;
    if (dma_isr_redir[10].dma_func)
      dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
  }

  /* Check on channel 5.*/
  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
  if (flags & STM32_DMA_ISR_MASK) {
    DMA2->IFCR = STM32_DMA_ISR_MASK << 16;
    if (dma_isr_redir[11].dma_func)
      dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
  }

  CH_IRQ_EPILOGUE();
}
#endif /* !STM32F10X_CL */
#endif /* STM32_HAS_DMA2 */

/*===========================================================================*/
/* Driver exported functions.                                                */
/*===========================================================================*/

/**
 * @brief   STM32 DMA helper initialization.
 *
 * @init
 */
void dmaInit(void) {
  int i;

  dma_streams_mask = 0;
  for (i = 0; i < STM32_DMA_STREAMS; i++) {
    _stm32_dma_streams[i].channel->CCR = 0;
    dma_isr_redir[i].dma_func = NULL;
  }
  DMA1->IFCR = 0xFFFFFFFF;
#if STM32_HAS_DMA2
  DMA2->IFCR = 0xFFFFFFFF;
#endif
}

/**
 * @brief   Allocates a DMA stream.
 * @details The stream is allocated and, if required, the DMA clock enabled.
 *          The function also enables the IRQ vector associated to the stream
 *          and initializes its priority.
 * @pre     The stream must not be already in use or an error is returned.
 * @post    The stream is allocated and the default ISR handler redirected
 *          to the specified function.
 * @post    The stream ISR vector is enabled and its priority configured.
 * @post    The stream must be freed using @p dmaStreamRelease() before it can
 *          be reused with another peripheral.
 * @post    The stream is in its post-reset state.
 * @note    This function can be invoked in both ISR or thread context.
 *
 * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
 * @param[in] priority  IRQ priority mask for the DMA stream
 * @param[in] func      handling function pointer, can be @p NULL
 * @param[in] param     a parameter to be passed to the handling function
 * @return              The operation status.
 * @retval FALSE        no error, stream taken.
 * @retval TRUE         error, stream already taken.
 *
 * @special
 */
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
                         uint32_t priority,
                         stm32_dmaisr_t func,
                         void *param) {

  chDbgCheck(dmastp != NULL, "dmaAllocate");

  /* Checks if the stream is already taken.*/
  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
    return TRUE;

  /* Marks the stream as allocated.*/
  dma_isr_redir[dmastp->selfindex].dma_func  = func;
  dma_isr_redir[dmastp->selfindex].dma_param = param;
  dma_streams_mask |= (1 << dmastp->selfindex);

  /* Enabling DMA clocks required by the current streams set.*/
  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
    rccEnableDMA1(FALSE);
#if STM32_HAS_DMA2
  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
    rccEnableDMA2(FALSE);
#endif

  /* Putting the stream in a safe state.*/
  dmaStreamDisable(dmastp);
  dmaStreamClearInterrupt(dmastp);
  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;

  /* Enables the associated IRQ vector if a callback is defined.*/
  if (func != NULL)
    NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));

  return FALSE;
}

/**
 * @brief   Releases a DMA stream.
 * @details The stream is freed and, if required, the DMA clock disabled.
 *          Trying to release a unallocated stream is an illegal operation
 *          and is trapped if assertions are enabled.
 * @pre     The stream must have been allocated using @p dmaStreamAllocate().
 * @post    The stream is again available.
 * @note    This function can be invoked in both ISR or thread context.
 *
 * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
 *
 * @special
 */
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

  chDbgCheck(dmastp != NULL, "dmaRelease");

  /* Check if the streams is not taken.*/
  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
              "dmaRelease(), #1", "not allocated");

  /* Disables the associated IRQ vector.*/
  NVICDisableVector(dmastp->vector);

  /* Marks the stream as not allocated.*/
  dma_streams_mask &= ~(1 << dmastp->selfindex);

  /* Shutting down clocks that are no more required, if any.*/
  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
    rccDisableDMA1(FALSE);
#if STM32_HAS_DMA2
  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
    rccDisableDMA2(FALSE);
#endif
}

#endif /* STM32_DMA_REQUIRED */

/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-24 04:23:28 +0000