/* ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ #ifndef MCUCONF_H #define MCUCONF_H /* * STM32F4xx drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the whole * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. */ #define STM32F4xx_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE #define STM32_LSE_ENABLED FALSE #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLM_VALUE 12 #define STM32_PLLN_VALUE 336 #define STM32_PLLP_VALUE 2 #define STM32_PLLQ_VALUE 7 #define STM32_HPRE STM32_HPRE_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV4 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE /* * ADC driver system settings. */ #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 #define STM32_ADC_USE_ADC1 FALSE #define STM32_ADC_USE_ADC2 FALSE #define STM32_ADC_USE_ADC3 FALSE #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_ADC_ADC1_DMA_PRIORITY 2 #define STM32_ADC_ADC2_DMA_PRIORITY 2 #define STM32_ADC_ADC3_DMA_PRIORITY 2 #define STM32_ADC_IRQ_PRIORITY 6 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. */ #define STM32_CAN_USE_CAN1 FALSE #define STM32_CAN_USE_CAN2 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 /* * DAC driver system settings. */ #define STM32_DAC_DUAL_MODE FALSE #define STM32_DAC_USE_DAC1_CH1 FALSE #define STM32_DAC_USE_DAC1_CH2 FALSE #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) /* * EXT driver system settings. */ #define STM32_EXT_EXTI0_IRQ_PRIORITY 6 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15 /* * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM6 FALSE #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE #define STM32_GPT_USE_TIM9 FALSE #define STM32_GPT_USE_TIM11 FALSE #define STM32_GPT_USE_TIM12 FALSE #define STM32_GPT_USE_TIM14 FALSE #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #define STM32_GPT_TIM6_IRQ_PRIORITY 7 #define STM32_GPT_TIM7_IRQ_PRIORITY 7 #define STM32_GPT_TIM8_IRQ_PRIORITY 7 #define STM32_GPT_TIM9_IRQ_PRIORITY 7 #define STM32_GPT_TIM11_IRQ_PRIORITY 7 #define STM32_GPT_TIM12_IRQ_PRIORITY 7 #define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. */ #define STM32_I2C_USE_I2C1 FALSE #define STM32_I2C_USE_I2C2 FALSE #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 #define STM32_I2C_I2C1_DMA_PRIORITY 3 #define STM32_I2C_I2C2_DMA_PRIORITY 3 #define STM32_I2C_I2C3_DMA_PRIORITY 3 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * I2S driver system settings. */ #define STM32_I2S_USE_SPI2 FALSE #define STM32_I2S_USE_SPI3 FALSE #define STM32_I2S_SPI2_IRQ_PRIORITY 10 #define STM32_I2S_SPI3_IRQ_PRIORITY 10 #define STM32_I2S_SPI2_DMA_PRIORITY 1 #define STM32_I2S_SPI3_DMA_PRIORITY 1 #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE #define STM32_ICU_USE_TIM3 FALSE #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM9 FALSE #define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 #define STM32_ICU_TIM3_IRQ_PRIORITY 7 #define STM32_ICU_TIM4_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM9_IRQ_PRIORITY 7 /* * MAC driver system settings. */ #define STM32_MAC_TRANSMIT_BUFFERS 2 #define STM32_MAC_RECEIVE_BUFFERS 4 #define STM32_MAC_BUFFERS_SIZE 1522 #define STM32_MAC_PHY_TIMEOUT 100 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE #define STM32_MAC_ETH1_IRQ_PRIORITY 13 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 /* * PWM driver system settings. */ #define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 #define STM32_PWM_TIM4_IRQ_PRIORITY 7 #define STM32_PWM_TIM5_IRQ_PRIORITY 7 #define STM32_PWM_TIM8_IRQ_PRIORITY 7 #define STM32_PWM_TIM9_IRQ_PRIORITY 7 /* * SDC driver system settings. */ #define STM32_SDC_SDIO_DMA_PRIORITY 3 #define STM32_SDC_SDIO_IRQ_PRIORITY 9 #define STM32_SDC_WRITE_TIMEOUT_MS 1000 #define STM32_SDC_READ_TIMEOUT_MS 1000 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) /* * SERIAL driver system settings. */ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART3 FALSE #define STM32_SERIAL_USE_UART4 FALSE #define STM32_SERIAL_USE_UART5 FALSE #define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USART1_PRIORITY 12 #define STM32_SERIAL_USART2_PRIORITY 12 #define STM32_SERIAL_USART3_PRIORITY 12 #define STM32_SERIAL_UART4_PRIORITY 12 #define STM32_SERIAL_UART5_PRIORITY 12 #define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. */ #define STM32_SPI_USE_SPI1 FALSE #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* * ST driver system settings. */ #define STM32_ST_IRQ_PRIORITY 8 #define STM32_ST_USE_TIMER 2 /* * UART driver system settings. */ #define STM32_UART_USE_USART1 FALSE #define STM32_UART_USE_USART2 FALSE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USE_UART4 FALSE #define STM32_UART_USE_UART5 FALSE #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 #define STM32_UART_UART4_IRQ_PRIORITY 12 #define STM32_UART_UART5_IRQ_PRIORITY 12 #define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 #define STM32_UART_UART4_DMA_PRIORITY 0 #define STM32_UART_UART5_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. */ #define STM32_USB_USE_OTG1 TRUE #define STM32_USB_USE_OTG2 TRUE #define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG2_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO #define STM32_USB_OTG_THREAD_STACK_SIZE 128 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0 /* * WDG driver system settings. */ #define STM32_WDG_USE_IWDG FALSE #endif /* MCUCONF_H */ n327'>327 328 329 330 331 332 333 334 335 336 337 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/*
 *      linux/arch/i386/kernel/irq.c
 *
 *      Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file contains the code used by various IRQ handling routines:
 * asking for different IRQ's should be done through these routines
 * instead of just grabbing them. Thus setup_irqs with different IRQ numbers
 * shouldn't result in any weird surprises, and installing new handlers
 * should be easier.
 */

/*
 * (mostly architecture independent, will move to kernel/irq.c in 2.5.)
 *
 * IRQs are in fact implemented a bit like signal handlers for the kernel.
 * Naturally it's not a 1:1 relation, but there are similarities.
 */

#include <xen/config.h>
#include <xen/init.h>
#include <xen/errno.h>
#include <xen/sched.h>
#include <xen/interrupt.h>
#include <xen/irq.h>
#include <xen/slab.h>
#include <xen/event.h>
#include <asm/mpspec.h>
#include <asm/io_apic.h>
#include <asm/msr.h>
#include <asm/hardirq.h>
#include <asm/ptrace.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <asm/pgalloc.h>
#include <xen/delay.h>
#include <xen/timex.h>
#include <xen/perfc.h>
#include <asm/smpboot.h>

/*
 * Linux has a controller-independent x86 interrupt architecture.
 * every controller has a 'controller-template', that is used
 * by the main code to do the right thing. Each driver-visible
 * interrupt source is transparently wired to the apropriate
 * controller. Thus drivers need not be aware of the
 * interrupt-controller.
 *
 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
 * (IO-APICs assumed to be messaging to Pentium local-APICs)
 *
 * the code is designed to be easily extended with new/different
 * interrupt controllers, without having to do assembly magic.
 */

/*
 * Controller mappings for all interrupt sources:
 */
irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned =
{ [0 ... NR_IRQS-1] = { 0, &no_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};

#ifdef CONFIG_SMP
/* NB. XXX We'll want some way of fiddling with this from DOM0. */
unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
#endif

static void __do_IRQ_guest(int irq);

/*
 * Special irq handlers.
 */

void no_action(int cpl, void *dev_id, struct pt_regs *regs) { }

/*
 * Generic no controller code
 */

static void enable_none(unsigned int irq) { }
static unsigned int startup_none(unsigned int irq) { return 0; }
static void disable_none(unsigned int irq) { }
static void ack_none(unsigned int irq)
{
/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves, it doesnt deserve
 * a generic callback i think.
 */
#if CONFIG_X86
    printk("unexpected IRQ trap at vector %02x\n", irq);
#ifdef CONFIG_X86_LOCAL_APIC
    /*
         * Currently unexpected vectors happen only on SMP and APIC.
         * We _must_ ack these because every local APIC has only N
         * irq slots per priority level, and a 'hanging, unacked' IRQ
         * holds up an irq slot - in excessive cases (when multiple
         * unexpected vectors occur) that might lock up the APIC
         * completely.
         */
    ack_APIC_irq();
#endif
#endif
}

/* startup is the same as "enable", shutdown is same as "disable" */
#define shutdown_none   disable_none
#define end_none        enable_none

struct hw_interrupt_type no_irq_type = {
    "none",
    startup_none,
    shutdown_none,
    enable_none,
    disable_none,
    ack_none,
    end_none
};

atomic_t irq_err_count;
#ifdef CONFIG_X86_IO_APIC
#ifdef APIC_MISMATCH_DEBUG
atomic_t irq_mis_count;
#endif
#endif

/*
 * Generic, controller-independent functions:
 */

/*
 * Global interrupt locks for SMP. Allow interrupts to come in on any
 * CPU, yet make cli/sti act globally to protect critical regions..
 */

#ifdef CONFIG_SMP
unsigned char global_irq_holder = 0xff;
unsigned volatile long global_irq_lock; /* pendantic: long for set_bit --RR */
        
#define MAXCOUNT 100000000

/*
 * I had a lockup scenario where a tight loop doing
 * spin_unlock()/spin_lock() on CPU#1 was racing with
 * spin_lock() on CPU#0. CPU#0 should have noticed spin_unlock(), but
 * apparently the spin_unlock() information did not make it
 * through to CPU#0 ... nasty, is this by design, do we have to limit
 * 'memory update oscillation frequency' artificially like here?
 *
 * Such 'high frequency update' races can be avoided by careful design, but
 * some of our major constructs like spinlocks use similar techniques,
 * it would be nice to clarify this issue. Set this define to 0 if you
 * want to check whether your system freezes.  I suspect the delay done
 * by SYNC_OTHER_CORES() is in correlation with 'snooping latency', but
 * i thought that such things are guaranteed by design, since we use
 * the 'LOCK' prefix.
 */
#define SUSPECTED_CPU_OR_CHIPSET_BUG_WORKAROUND 0

#if SUSPECTED_CPU_OR_CHIPSET_BUG_WORKAROUND
# define SYNC_OTHER_CORES(x) udelay(x+1)
#else
/*
 * We have to allow irqs to arrive between __sti and __cli
 */
# define SYNC_OTHER_CORES(x) __asm__ __volatile__ ("nop")
#endif

static inline void wait_on_irq(int cpu)
{
    for (;;) {

        /*
         * Wait until all interrupts are gone. Wait
         * for bottom half handlers unless we're
         * already executing in one..
         */
        if (!irqs_running())
            if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock))
                break;

        /* Duh, we have to loop. Release the lock to avoid deadlocks */
        clear_bit(0,&global_irq_lock);

        for (;;) {
            __sti();
            SYNC_OTHER_CORES(cpu);
            __cli();
            if (irqs_running())
                continue;
            if (global_irq_lock)
                continue;
            if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock))
                continue;
            if (!test_and_set_bit(0,&global_irq_lock))
                break;
        }
    }
}

/*
 * This is called when we want to synchronize with
 * interrupts. We may for example tell a device to
 * stop sending interrupts: but to make sure there
 * are no interrupts that are executing on another
 * CPU we need to call this function.
 */
void synchronize_irq(void)
{
    if (irqs_running()) {
        /* Stupid approach */
        cli();
        sti();
    }
}

static inline void get_irqlock(int cpu)
{
    if (test_and_set_bit(0,&global_irq_lock)) {
        /* do we already hold the lock? */
        if ((unsigned char) cpu == global_irq_holder)
            return;
        /* Uhhuh.. Somebody else got it. Wait.. */
        do {
            do {
                rep_nop();
            } while (test_bit(0,&global_irq_lock));
        } while (test_and_set_bit(0,&global_irq_lock));         
    }
    /* 
     * We also to make sure that nobody else is running
     * in an interrupt context. 
     */
    wait_on_irq(cpu);

    /*
     * Ok, finally..
     */
    global_irq_holder = cpu;
}

#define EFLAGS_IF_SHIFT 9

/*
 * A global "cli()" while in an interrupt context
 * turns into just a local cli(). Interrupts
 * should use spinlocks for the (very unlikely)
 * case that they ever want to protect against
 * each other.
 *
 * If we already have local interrupts disabled,
 * this will not turn a local disable into a
 * global one (problems with spinlocks: this makes
 * save_flags+cli+sti usable inside a spinlock).
 */
void __global_cli(void)
{
    unsigned int flags;

    __save_flags(flags);
    if (flags & (1 << EFLAGS_IF_SHIFT)) {
        int cpu = smp_processor_id();
        __cli();
        if (!local_irq_count(cpu))
            get_irqlock(cpu);
    }
}

void __global_sti(void)
{
    int cpu = smp_processor_id();

    if (!local_irq_count(cpu))
        release_irqlock(cpu);
    __sti();
}

/*
 * SMP flags value to restore to:
 * 0 - global cli
 * 1 - global sti
 * 2 - local cli
 * 3 - local sti
 */
unsigned long __global_save_flags(void)
{
    int retval;
    int local_enabled;
    unsigned long flags;
    int cpu = smp_processor_id();

    __save_flags(flags);
    local_enabled = (flags >> EFLAGS_IF_SHIFT) & 1;
    /* default to local */
    retval = 2 + local_enabled;

    /* check for global flags if we're not in an interrupt */
    if (!local_irq_count(cpu)) {
        if (local_enabled)
            retval = 1;
        if (global_irq_holder == cpu)
            retval = 0;
    }
    return retval;
}

void __global_restore_flags(unsigned long flags)
{
    switch (flags) {
    case 0:
        __global_cli();
        break;
    case 1:
        __global_sti();
        break;
    case 2:
        __cli();
        break;
    case 3:
        __sti();
        break;
    default:
        printk("global_restore_flags: %08lx (%08lx)\n",
               flags, (&flags)[-1]);
    }
}

#endif

/*
 * This should really return information about whether
 * we should do bottom half handling etc. Right now we
 * end up _always_ checking the bottom half, which is a
 * waste of time and is not what some drivers would
 * prefer.
 */
static int handle_IRQ_event(unsigned int irq, 
                            struct pt_regs * regs, 
                            struct irqaction * action)
{
    int status;
    int cpu = smp_processor_id();

    irq_enter(cpu, irq);

    status = 1; /* Force the "do bottom halves" bit */

    if (!(action->flags & SA_INTERRUPT))
        __sti();

    do {
        status |= action->flags;
        action->handler(irq, action->dev_id, regs);
        action = action->next;
    } while (action);

    __cli();

    irq_exit(cpu, irq);

    return status;
}

/*
 * Generic enable/disable code: this just calls
 * down into the PIC-specific version for the actual
 * hardware disable after having gotten the irq
 * controller lock. 
 */
 
/**
 *      disable_irq_nosync - disable an irq without waiting
 *      @irq: Interrupt to disable
 *
 *      Disable the selected interrupt line.  Disables and Enables are
 *      nested.
 *      Unlike disable_irq(), this function does not ensure existing
 *      instances of the IRQ handler have completed before returning.
 *
 *      This function may be called from IRQ context.
 */
 
inline void disable_irq_nosync(unsigned int irq)
{
    irq_desc_t *desc = irq_desc + irq;
    unsigned long flags;

    spin_lock_irqsave(&desc->lock, flags);
    if (!desc->depth++) {
        desc->status |= IRQ_DISABLED;
        desc->handler->disable(irq);
    }
    spin_unlock_irqrestore(&desc->lock, flags);
}

/**
 *      disable_irq - disable an irq and wait for completion
 *      @irq: Interrupt to disable
 *
 *      Disable the selected interrupt line.  Enables and Disables are
 *      nested.
 *      This function waits for any pending IRQ handlers for this interrupt
 *      to complete before returning. If you use this function while
 *      holding a resource the IRQ handler may need you will deadlock.
 *
 *      This function may be called - with care - from IRQ context.
 */
 
void disable_irq(unsigned int irq)
{
    disable_irq_nosync(irq);

    if (!local_irq_count(smp_processor_id())) {
        do {
            barrier();
            cpu_relax();
        } while (irq_desc[irq].status & IRQ_INPROGRESS);
    }
}

/**
 *      enable_irq - enable handling of an irq
 *      @irq: Interrupt to enable
 *
 *      Undoes the effect of one call to disable_irq().  If this
 *      matches the last disable, processing of interrupts on this
 *      IRQ line is re-enabled.
 *
 *      This function may be called from IRQ context.
 */
 
void enable_irq(unsigned int irq)
{
    irq_desc_t *desc = irq_desc + irq;
    unsigned long flags;

    spin_lock_irqsave(&desc->lock, flags);
    switch (desc->depth) {
    case 1: {
        unsigned int status = desc->status & ~IRQ_DISABLED;
        desc->status = status;
        if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
            desc->status = status | IRQ_REPLAY;
            hw_resend_irq(desc->handler,irq);
        }
        desc->handler->enable(irq);
        /* fall-through */
    }
    default:
        desc->depth--;
        break;
    case 0:
        printk("enable_irq(%u) unbalanced from %p\n", irq,
               __builtin_return_address(0));
    }
    spin_unlock_irqrestore(&desc->lock, flags);
}

/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
asmlinkage unsigned int do_IRQ(struct pt_regs regs)
{       
    /* 
     * We ack quickly, we don't want the irq controller
     * thinking we're snobs just because some other CPU has
     * disabled global interrupts (we have already done the
     * INT_ACK cycles, it's too late to try to pretend to the
     * controller that we aren't taking the interrupt).
     *
     * 0 return value means that this irq is already being
     * handled by some other CPU. (or is disabled)
     */
    int irq = regs.orig_eax & 0xff; /* high bits used in ret_from_ code  */
    irq_desc_t *desc = irq_desc + irq;
    struct irqaction * action;
    unsigned int status;

#ifdef PERF_COUNTERS
    int cpu = smp_processor_id();
    u32 cc_start, cc_end;

    perfc_incra(irqs, cpu);
    rdtscl(cc_start);
#endif

    spin_lock(&desc->lock);
    desc->handler->ack(irq);

    /*
      REPLAY is when Linux resends an IRQ that was dropped earlier
      WAITING is used by probe to mark irqs that are being tested
    */
    status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
    status |= IRQ_PENDING; /* we _want_ to handle it */

    /* We hook off guest-bound IRQs for special handling. */
    if ( status & IRQ_GUEST )
    {
        __do_IRQ_guest(irq);
        spin_unlock(&desc->lock);
        return 1;
    }

    /*
     * If the IRQ is disabled for whatever reason, we cannot use the action we 
     * have.
     */
    action = NULL;
    if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
        action = desc->action;
        status &= ~IRQ_PENDING; /* we commit to handling */
        status |= IRQ_INPROGRESS; /* we are handling it */
    }
    desc->status = status;

    /*
     * If there is no IRQ handler or it was disabled, exit early. Since we set 
     * PENDING, if another processor is handling a different instance of this 
     * same irq, the other processor will take care of it.
     */
    if (!action)
        goto out;

    /*
     * Edge triggered interrupts need to remember pending events. This applies 
     * to any hw interrupts that allow a second instance of the same irq to 
     * arrive while we are in do_IRQ or in the handler. But the code here only 
     * handles the _second_ instance of the irq, not the third or fourth. So 
     * it is mostly useful for irq hardware that does not mask cleanly in an
     * SMP environment.
     */
    for (;;) {
        spin_unlock(&desc->lock);
        handle_IRQ_event(irq, &regs, action);
        spin_lock(&desc->lock);
                
        if (!(desc->status & IRQ_PENDING))
            break;
        desc->status &= ~IRQ_PENDING;
    }
    desc->status &= ~IRQ_INPROGRESS;
 out:
    /*
     * The ->end() handler has to deal with interrupts which got disabled 
     * while the handler was running.
     */
    desc->handler->end(irq);
    spin_unlock(&desc->lock);

#ifdef PERF_COUNTERS
    rdtscl(cc_end);

    if ( !action || (!(action->flags & SA_NOPROFILE)) )
    {
        perfc_adda(irq_time, cpu, cc_end - cc_start);
#ifndef NDEBUG
        if ( (cc_end - cc_start) > (cpu_khz * 100) )
            printk("Long interrupt %08x -> %08x\n", cc_start, cc_end);
#endif
    }
#endif

    return 1;
}

/**
 *      request_irq - allocate an interrupt line
 *      @irq: Interrupt line to allocate
 *      @handler: Function to be called when the IRQ occurs
 *      @irqflags: Interrupt type flags
 *      @devname: An ascii name for the claiming device
 *      @dev_id: A cookie passed back to the handler function
 *
 *      This call allocates interrupt resources and enables the
 *      interrupt line and IRQ handling. From the point this
 *      call is made your handler function may be invoked. Since
 *      your handler function must clear any interrupt the board 
 *      raises, you must take care both to initialise your hardware
 *      and to set up the interrupt handler in the right order.
 *
 *      Dev_id must be globally unique. Normally the address of the
 *      device data structure is used as the cookie. Since the handler
 *      receives this value it makes sense to use it.
 *
 *      If your interrupt is shared you must pass a non NULL dev_id
 *      as this is required when freeing the interrupt.
 *
 *      Flags:
 *
 *      SA_SHIRQ                Interrupt is shared
 *
 *      SA_INTERRUPT            Disable local interrupts while processing
 */
 
int request_irq(unsigned int irq, 
                void (*handler)(int, void *, struct pt_regs *),
                unsigned long irqflags, 
                const char * devname,
                void *dev_id)
{
    int retval;
    struct irqaction * action;

    if (irq >= NR_IRQS)
        return -EINVAL;
    if (!handler)
        return -EINVAL;

    action = (struct irqaction *)
        kmalloc(sizeof(struct irqaction), GFP_KERNEL);
    if (!action)
        return -ENOMEM;

    action->handler = handler;
    action->flags = irqflags;
    action->mask = 0;
    action->name = devname;
    action->next = NULL;
    action->dev_id = dev_id;

    retval = setup_irq(irq, action);
    if (retval)
        kfree(action);

    return retval;
}

/**
 *      free_irq - free an interrupt
 *      @irq: Interrupt line to free
 *      @dev_id: Device identity to free
 *
 *      Remove an interrupt handler. The handler is removed and if the
 *      interrupt line is no longer in use by any driver it is disabled.
 *      On a shared IRQ the caller must ensure the interrupt is disabled
 *      on the card it drives before calling this function. The function
 *      does not return until any executing interrupts for this IRQ
 *      have completed.
 *
 *      This function may be called from interrupt context. 
 *
 *      Bugs: Attempting to free an irq in a handler for the same irq hangs
 *            the machine.
 */
 
void free_irq(unsigned int irq, void *dev_id)
{
    irq_desc_t *desc;
    struct irqaction **p;
    unsigned long flags;

    if (irq >= NR_IRQS)
        return;

    desc = irq_desc + irq;
    spin_lock_irqsave(&desc->lock,flags);
    p = &desc->action;
    for (;;) {
        struct irqaction * action = *p;
        if (action) {
            struct irqaction **pp = p;
            p = &action->next;
            if (action->dev_id != dev_id)
                continue;

            /* Found it - now remove it from the list of entries */
            *pp = action->next;
            if (!desc->action) {
                desc->status |= IRQ_DISABLED;
                desc->handler->shutdown(irq);
            }
            spin_unlock_irqrestore(&desc->lock,flags);

#ifdef CONFIG_SMP
            /* Wait to make sure it's not being used on another CPU */
            while (desc->status & IRQ_INPROGRESS) {
                barrier();
                cpu_relax();
            }
#endif
            kfree(action);
            return;
        }
        printk("Trying to free free IRQ%d\n",irq);
        spin_unlock_irqrestore(&desc->lock,flags);
        return;
    }
}

/*
 * IRQ autodetection code..
 *
 * This depends on the fact that any interrupt that
 * comes in on to an unassigned handler will get stuck
 * with "IRQ_WAITING" cleared and the interrupt
 * disabled.
 */

static spinlock_t probe_sem = SPIN_LOCK_UNLOCKED;

/**
 *      probe_irq_on    - begin an interrupt autodetect
 *
 *      Commence probing for an interrupt. The interrupts are scanned
 *      and a mask of potential interrupt lines is returned.
 *
 */
 
unsigned long probe_irq_on(void)
{
    unsigned int i;
    irq_desc_t *desc;
    unsigned long val;
    unsigned long s=0, e=0;

    spin_lock(&probe_sem);
    /* 
     * something may have generated an irq long ago and we want to
     * flush such a longstanding irq before considering it as spurious. 
     */
    for (i = NR_IRQS-1; i > 0; i--)  {
        desc = irq_desc + i;

        spin_lock_irq(&desc->lock);
        if (!irq_desc[i].action) 
            irq_desc[i].handler->startup(i);
        spin_unlock_irq(&desc->lock);
    }

    /* Wait for longstanding interrupts to trigger (20ms delay). */
    rdtscl(s);
    do {
        synchronize_irq();
        rdtscl(e);
    } while ( ((e-s)/ticks_per_usec) < 20000 );

    /*
     * enable any unassigned irqs
     * (we must startup again here because if a longstanding irq
     * happened in the previous stage, it may have masked itself)
     */
    for (i = NR_IRQS-1; i > 0; i--) {
        desc = irq_desc + i;

        spin_lock_irq(&desc->lock);
        if (!desc->action) {
            desc->status |= IRQ_AUTODETECT | IRQ_WAITING;
            if (desc->handler->startup(i))
                desc->status |= IRQ_PENDING;
        }
        spin_unlock_irq(&desc->lock);
    }

    /*
     * Wait for spurious interrupts to trigger (100ms delay). 
     */
    rdtscl(s);
    do {
        synchronize_irq();
        rdtscl(e);
    } while ( ((e-s)/ticks_per_usec) < 100000 );

    /*
     * Now filter out any obviously spurious interrupts
     */
    val = 0;
    for (i = 0; i < NR_IRQS; i++) {
        irq_desc_t *desc = irq_desc + i;
        unsigned int status;

        spin_lock_irq(&desc->lock);
        status = desc->status;

        if (status & IRQ_AUTODETECT) {
            /* It triggered already - consider it spurious. */
            if (!(status & IRQ_WAITING)) {
                desc->status = status & ~IRQ_AUTODETECT;
                desc->handler->shutdown(i);
            } else
                if (i < 32)
                    val |= 1 << i;
        }
        spin_unlock_irq(&desc->lock);
    }

    return val;
}

/*
 * Return a mask of triggered interrupts (this
 * can handle only legacy ISA interrupts).
 */
 
/**
 *      probe_irq_mask - scan a bitmap of interrupt lines
 *      @val:   mask of interrupts to consider
 *
 *      Scan the ISA bus interrupt lines and return a bitmap of
 *      active interrupts. The interrupt probe logic state is then
 *      returned to its previous value.
 *
 *      Note: we need to scan all the irq's even though we will
 *      only return ISA irq numbers - just so that we reset them
 *      all to a known state.
 */
unsigned int probe_irq_mask(unsigned long val)
{
    int i;
    unsigned int mask;

    mask = 0;
    for (i = 0; i < NR_IRQS; i++) {
        irq_desc_t *desc = irq_desc + i;
        unsigned int status;

        spin_lock_irq(&desc->lock);
        status = desc->status;

        if (status & IRQ_AUTODETECT) {
            if (i < 16 && !(status & IRQ_WAITING))
                mask |= 1 << i;

            desc->status = status & ~IRQ_AUTODETECT;
            desc->handler->shutdown(i);
        }
        spin_unlock_irq(&desc->lock);
    }
    spin_unlock(&probe_sem);

    return mask & val;
}

/*
 * Return the one interrupt that triggered (this can
 * handle any interrupt source).
 */

/**
 *      probe_irq_off   - end an interrupt autodetect
 *      @val: mask of potential interrupts (unused)
 *
 *      Scans the unused interrupt lines and returns the line which
 *      appears to have triggered the interrupt. If no interrupt was
 *      found then zero is returned. If more than one interrupt is
 *      found then minus the first candidate is returned to indicate
 *      their is doubt.
 *
 *      The interrupt probe logic state is returned to its previous
 *      value.
 *
 *      BUGS: When used in a module (which arguably shouldnt happen)
 *      nothing prevents two IRQ probe callers from overlapping. The
 *      results of this are non-optimal.
 */
 
int probe_irq_off(unsigned long val)
{
    int i, irq_found, nr_irqs;

    nr_irqs = 0;
    irq_found = 0;
    for (i = 0; i < NR_IRQS; i++) {
        irq_desc_t *desc = irq_desc + i;
        unsigned int status;

        spin_lock_irq(&desc->lock);
        status = desc->status;

        if (status & IRQ_AUTODETECT) {
            if (!(status & IRQ_WAITING)) {
                if (!nr_irqs)
                    irq_found = i;
                nr_irqs++;
            }
            desc->status = status & ~IRQ_AUTODETECT;
            desc->handler->shutdown(i);
        }
        spin_unlock_irq(&desc->lock);
    }
    spin_unlock(&probe_sem);

    if (nr_irqs > 1)
        irq_found = -irq_found;
    return irq_found;
}

/* this was setup_x86_irq but it seems pretty generic */
int setup_irq(unsigned int irq, struct irqaction * new)
{
    int shared = 0;
    unsigned long flags;
    struct irqaction *old, **p;
    irq_desc_t *desc = irq_desc + irq;

    /*
     * The following block of code has to be executed atomically
     */
    spin_lock_irqsave(&desc->lock,flags);

    if ( desc->status & IRQ_GUEST )
    {
        spin_unlock_irqrestore(&desc->lock,flags);
        return -EBUSY;
    }

    p = &desc->action;
    if ((old = *p) != NULL) {