/** ****************************************************************************** * @file stm32l1xx.h * @author MCD Application Team * @version V1.0.0 * @date 31-December-2010 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2010 STMicroelectronics

****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32l1xx * @{ */ #ifndef __STM32L1XX_H #define __STM32L1XX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Library_configuration_section * @{ */ /* Uncomment the line below according to the target STM32L device used in your application */ #if !defined (STM32L1XX_MD) #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. */ #if !defined (STM32L1XX_MD) #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" #endif #if !defined USE_STDPERIPH_DRIVER /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_STDPERIPH_DRIVER*/ #endif /** * @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ /** * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup Timeout value */ #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature. */ #define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ /** * @brief STM32L1xx Standard Peripheral Library version number */ #define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ |(__STM32L1XX_STDPERIPH_VERSION_RC)) /** * @} */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief STM32L1xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ #define __MPU_PRESENT 1 /*!< STM32L provides MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /*!< Interrupt Number Definition */ typedef enum IRQn { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ /****** STM32L specific Interrupt Numbers ***********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ DAC_IRQn = 21, /*!< DAC Interrupt */ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ LCD_IRQn = 24, /*!< LCD Interrupt */ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm3.h" /* CHIBIOS FIX */ /*#include "system_stm32l1xx.h"*/ #include /** @addtogroup Exported_types * @{ */ typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; /** * @brief __RAM_FUNC definition */ #if defined ( __CC_ARM ) /* ARM Compiler ------------ RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ #define __RAM_FUNC FLASH_Status #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc FLASH_Status #elif defined ( __GNUC__ ) /* GNU Compiler ------------ RAM functions are defined using a specific toolchain attribute "__attribute__((section(".data")))". */ #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) #elif defined ( __TASKING__ ) /* TASKING Compiler ---------------- RAM functions are defined using a specific toolchain pragma. This pragma is defined in the stm32l1xx_flash_ramfunc.c */ #define __RAM_FUNC FLASH_Status #endif /** * @} */ /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t SMPR1; __IO uint32_t SMPR2; __IO uint32_t SMPR3; __IO uint32_t JOFR1; __IO uint32_t JOFR2; __IO uint32_t JOFR3; __IO uint32_t JOFR4; __IO uint32_t HTR; __IO uint32_t LTR; __IO uint32_t SQR1; __IO uint32_t SQR2; __IO uint32_t SQR3; __IO uint32_t SQR4; __IO uint32_t SQR5; __IO uint32_t JSQR; __IO uint32_t JDR1; __IO uint32_t JDR2; __IO uint32_t JDR3; __IO uint32_t JDR4; __IO uint32_t DR; } ADC_TypeDef; typedef struct { __IO uint32_t CSR; __IO uint32_t CCR; } ADC_Common_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; } COMP_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; __IO uint8_t IDR; uint8_t RESERVED0; uint16_t RESERVED1; __IO uint32_t CR; } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; __IO uint32_t SWTRIGR; __IO uint32_t DHR12R1; __IO uint32_t DHR12L1; __IO uint32_t DHR8R1; __IO uint32_t DHR12R2; __IO uint32_t DHR12L2; __IO uint32_t DHR8R2; __IO uint32_t DHR12RD; __IO uint32_t DHR12LD; __IO uint32_t DHR8RD; __IO uint32_t DOR1; __IO uint32_t DOR2; __IO uint32_t SR; } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; __IO uint32_t CR; __IO uint32_t APB1FZ; __IO uint32_t APB2FZ; }DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; __IO uint32_t CNDTR; __IO uint32_t CPAR; __IO uint32_t CMAR; } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; __IO uint32_t IFCR; } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; __IO uint32_t EMR; __IO uint32_t RTSR; __IO uint32_t FTSR; __IO uint32_t SWIER; __IO uint32_t PR; } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; __IO uint32_t PECR; __IO uint32_t PDKEYR; __IO uint32_t PEKEYR; __IO uint32_t PRGKEYR; __IO uint32_t OPTKEYR; __IO uint32_t SR; __IO uint32_t OBR; __IO uint32_t WRPR; } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint32_t RDP; __IO uint32_t USER; __IO uint32_t WRP01; __IO uint32_t WRP23; } OB_TypeDef; /** * @brief General Purpose IO */ /* CHIBIOS FIX */ #if 0 typedef struct { __IO uint32_t MODER; __IO uint16_t OTYPER; uint16_t RESERVED0; __IO uint32_t OSPEEDR; __IO uint32_t PUPDR; __IO uint16_t IDR; uint16_t RESERVED1; __IO uint16_t ODR; uint16_t RESERVED2; __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ __IO uint32_t LCKR; __IO uint32_t AFR[2]; } GPIO_TypeDef; #endif /** * @brief SysTem Configuration */ typedef struct { __IO uint32_t MEMRMP; __IO uint32_t PMC; __IO uint32_t EXTICR[4]; } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t OAR1; uint16_t RESERVED2; __IO uint16_t OAR2; uint16_t RESERVED3; __IO uint16_t DR; uint16_t RESERVED4; __IO uint16_t SR1; uint16_t RESERVED5; __IO uint16_t SR2; uint16_t RESERVED6; __IO uint16_t CCR; uint16_t RESERVED7; __IO uint16_t TRISE; uint16_t RESERVED8; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; __IO uint32_t PR; __IO uint32_t RLR; __IO uint32_t SR; } IWDG_TypeDef; /** * @brief LCD */ typedef struct { __IO uint32_t CR; __IO uint32_t FCR; __IO uint32_t SR; __IO uint32_t CLR; uint32_t RESERVED; __IO uint32_t RAM[16]; } LCD_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; __IO uint32_t CSR; } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; __IO uint32_t ICSCR; __IO uint32_t CFGR; __IO uint32_t CIR; __IO uint32_t AHBRSTR; __IO uint32_t APB2RSTR; __IO uint32_t APB1RSTR; __IO uint32_t AHBENR; __IO uint32_t APB2ENR; __IO uint32_t APB1ENR; __IO uint32_t AHBLPENR; __IO uint32_t APB2LPENR; __IO uint32_t APB1LPENR; __IO uint32_t CSR; } RCC_TypeDef; /** * @brief Routing Interface */ typedef struct { __IO uint32_t ICR; __IO uint32_t ASCR1; __IO uint32_t ASCR2; __IO uint32_t HYSCR1; __IO uint32_t HYSCR2; __IO uint32_t HYSCR3; } RI_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; __IO uint32_t DR; __IO uint32_t CR; __IO uint32_t ISR; __IO uint32_t PRER; __IO uint32_t WUTR; __IO uint32_t CALIBR; __IO uint32_t ALRMAR; __IO uint32_t ALRMBR; __IO uint32_t WPR; uint32_t RESERVED1; uint32_t RESERVED2; __IO uint32_t TSTR; __IO uint32_t TSDR; uint32_t RESERVED3; uint32_t RESERVED4; __IO uint32_t TAFCR; uint32_t RESERVED5; uint32_t RESERVED6; uint32_t RESERVED7; __IO uint32_t BKP0R; __IO uint32_t BKP1R; __IO uint32_t BKP2R; __IO uint32_t BKP3R; __IO uint32_t BKP4R; __IO uint32_t BKP5R; __IO uint32_t BKP6R; __IO uint32_t BKP7R; __IO uint32_t BKP8R; __IO uint32_t BKP9R; __IO uint32_t BKP10R; __IO uint32_t BKP11R; __IO uint32_t BKP12R; __IO uint32_t BKP13R; __IO uint32_t BKP14R; __IO uint32_t BKP15R; __IO uint32_t BKP16R; __IO uint32_t BKP17R; __IO uint32_t BKP18R; __IO uint32_t BKP19R; } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SR; uint16_t RESERVED2; __IO uint16_t DR; uint16_t RESERVED3; __IO uint16_t CRCPR; uint16_t RESERVED4; __IO uint16_t RXCRCR; uint16_t RESERVED5; __IO uint16_t TXCRCR; uint16_t RESERVED6; } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; uint16_t RESERVED0; __IO uint16_t CR2; uint16_t RESERVED1; __IO uint16_t SMCR; uint16_t RESERVED2; __IO uint16_t DIER; uint16_t RESERVED3; __IO uint16_t SR; uint16_t RESERVED4; __IO uint16_t EGR; uint16_t RESERVED5; __IO uint16_t CCMR1; uint16_t RESERVED6; __IO uint16_t CCMR2; uint16_t RESERVED7; __IO uint16_t CCER; uint16_t RESERVED8; __IO uint16_t CNT; uint16_t RESERVED9; __IO uint16_t PSC; uint16_t RESERVED10; __IO uint16_t ARR; uint16_t RESERVED11; uint32_t RESERVED12; __IO uint16_t CCR1; uint16_t RESERVED13; __IO uint16_t CCR2; uint16_t RESERVED14; __IO uint16_t CCR3; uint16_t RESERVED15; __IO uint16_t CCR4; uint16_t RESERVED16; uint32_t RESERVED17; __IO uint16_t DCR; uint16_t RESERVED18; __IO uint16_t DMAR; uint16_t RESERVED19; __IO uint16_t OR; uint16_t RESERVED20; } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t SR; uint16_t RESERVED0; __IO uint16_t DR; uint16_t RESERVED1; __IO uint16_t BRR; uint16_t RESERVED2; __IO uint16_t CR1; uint16_t RESERVED3; __IO uint16_t CR2; uint16_t RESERVED4; __IO uint16_t CR3; uint16_t RESERVED5; __IO uint16_t GTPR; uint16_t RESERVED6; } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; __IO uint32_t CFR; __IO uint32_t SR; } WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define LCD_BASE (APB1PERIPH_BASE + 0x2400) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) #define COMP_BASE (APB1PERIPH_BASE + 0x7C00) #define RI_BASE (APB1PERIPH_BASE + 0x7C04) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) #define TIM9_BASE (APB2PERIPH_BASE + 0x0800) #define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) #define TIM11_BASE (APB2PERIPH_BASE + 0x1000) #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) #define ADC_BASE (APB2PERIPH_BASE + 0x2700) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define USART1_BASE (APB2PERIPH_BASE + 0x3800) #define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) #define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) #define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) #define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) #define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) #define CRC_BASE (AHBPERIPH_BASE + 0x3000) #define RCC_BASE (AHBPERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ #define DMA1_BASE (AHBPERIPH_BASE + 0x6000) #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define LCD ((LCD_TypeDef *) LCD_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define COMP ((COMP_TypeDef *) COMP_BASE) #define RI ((RI_TypeDef *) RI_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ /******************* Bit definition for ADC_CR1 register ********************/ #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ /******************* Bit definition for ADC_CR2 register ********************/ #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ /****************** Bit definition for ADC_SMPR1 register *******************/ #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR2 register *******************/ #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ /****************** Bit definition for ADC_SMPR3 register *******************/ #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ /****************** Bit definition for ADC_JOFR2 register *******************/ #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ /****************** Bit definition for ADC_JOFR3 register *******************/ #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ /****************** Bit definition for ADC_JOFR4 register *******************/ #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ /******************* Bit definition for ADC_HTR register ********************/ #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ /******************* Bit definition for ADC_LTR register ********************/ #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ /******************* Bit definition for ADC_SQR2 register *******************/ #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR3 register *******************/ #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR4 register *******************/ #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ /******************* Bit definition for ADC_SQR5 register *******************/ #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ /******************* Bit definition for ADC_JSQR register *******************/ #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ /******************* Bit definition for ADC_JDR1 register *******************/ #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ /******************* Bit definition for ADC_JDR2 register *******************/ #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ /******************* Bit definition for ADC_JDR3 register *******************/ #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ /******************* Bit definition for ADC_JDR4 register *******************/ #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ /******************* Bit definition for ADC_CSR register ********************/ #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ /******************* Bit definition for ADC_CCR register ********************/ #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ /******************************************************************************/ /* */ /* Digital to Analog Converter (DAC) */ /* */ /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!