/* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. ChibiOS/RT is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ /** * @defgroup STM32F100_HAL STM32F100 HAL Support * @details HAL support for STM32 Value Line LD, MD and HD sub-families. * * @ingroup HAL */ /** * @file STM32/hal_lld_f100.h * @brief STM32F100 Value Line HAL subsystem low level driver header. * * @addtogroup STM32F100_HAL * @{ */ #ifndef _HAL_LLD_F100_H_ #define _HAL_LLD_F100_H_ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ #define STM32_HSICLK 8000000 /**< High speed internal clock. */ #define STM32_LSICLK 40000 /**< Low speed internal clock. */ /* RCC_CFGR register bits definitions.*/ #define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ #define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ #define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ #define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ #define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ #define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ #define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ #define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ #define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ #define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ #define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ #define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ #define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */ #define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */ #define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */ #define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ #define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ #define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ #define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ #define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ #define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ #define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */ #define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */ #define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */ #define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ #define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ #define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ #define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ #define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ #define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */ #define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */ /*===========================================================================*/ /* Platform specific friendly IRQ names. */ /*===========================================================================*/ #define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ #define PVD_IRQHandler Vector44 /**< PVD through EXTI Line detect. */ #define TAMPER_IRQHandler Vector48 /**< Tamper. */ #define RTC_IRQHandler Vector4C /**< RTC. */ #define FLASH_IRQHandler Vector50 /**< Flash. */ #define RCC_IRQHandler Vector54 /**< RCC. */ #define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ #define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ #define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ #define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ #define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ #define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ #define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ #define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ #define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ #define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ #define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ #define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ #define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ #define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ #define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ #define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ #define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and Commutation. */ #define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ #define TIM2_IRQHandler VectorB0 /**< TIM2. */ #define TIM3_IRQHandler VectorB4 /**< TIM3. */ #if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) #define TIM4_IRQHandler VectorB8 /**< TIM4. */ #endif #define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ #define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ #if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) #define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ #define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ #endif #define SPI1_IRQHandler VectorCC /**< SPI1. */ #if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) #define SPI2_IRQHandler VectorD0 /**< SPI2. */ #endif #define USART1_IRQHandler VectorD4 /**< USART1. */ #define USART2_IRQHandler VectorD8 /**< USART2. */ #if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) #define USART3_IRQHandler VectorDC /**< USART3. */ #endif #define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ #define RTCAlarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ #define CEC_IRQHandler VectorE8 /**< CEC. */ #define TIM12_IRQHandler VectorEC /**< TIM12. */ #define TIM13_IRQHandler VectorF0 /**< TIM13. */ #define TIM14_IRQHandler VectorF4 /**< TIM14. */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not * initialized and started. * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_SW) || defined(__DOXYGEN__) #define STM32_SW STM32_SW_PLL #endif /** * @brief Clock source for the PLL. * @note This setting has only effect if the PLL is selected as the * system clock source. * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) #define STM32_PLLSRC STM32_PLLSRC_HSE #endif /** * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the * system clock source. * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #endif /** * @brief PLL multiplier value. * @note The allowed range is 2...16. * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__) #define STM32_PLLMUL_VALUE 9 #endif /** * @brief AHB prescaler value. * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ #if !defined(STM32_HPRE) || defined(__DOXYGEN__) #define STM32_HPRE STM32_HPRE_DIV1 #endif /** * @brief APB1 prescaler value. */ #if !defined(STM32_PPRE1) || defined(__DOXYGEN__) #define STM32_PPRE1 STM32_PPRE1_DIV2 #endif /** * @brief APB2 prescaler value. */ #if !defined(STM32_PPRE2) || defined(__DOXYGEN__) #define STM32_PPRE2 STM32_PPRE2_DIV2 #endif /** * @brief ADC prescaler value. */ #if !defined(STM32_ADCPRE) || defined(__DOXYGEN__) #define STM32_ADCPRE STM32_ADCPRE_DIV4 #endif /** * @brief MCO pin setting. */ #if !defined(STM32_MCO) || defined(__DOXYGEN__) #define STM32_MCO STM32_MCO_NOCLOCK #endif /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ /* HSE prescaler setting check.*/ #if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) #error "invalid STM32_PLLXTPRE value specified" #endif /** * @brief PLLMUL field. */ #if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \ defined(__DOXYGEN__) #define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18) #else #error "invalid STM32_PLLMUL_VALUE value specified" #endif /** * @brief PLL input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) #if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 #define STM32_PLLCLKIN (STM32_HSECLK / 1) #else #define STM32_PLLCLKIN (STM32_HSECLK / 2) #endif #elif STM32_PLLSRC == STM32_PLLSRC_HSI #define STM32_PLLCLKIN (STM32_HSICLK / 2) #else #error "invalid STM32_PLLSRC value specified" #endif /* PLL input frequency range check.*/ #if (STM32_PLLCLKIN < 1000000) || (STM32_PLLCLKIN > 24000000) #error "STM32_PLLCLKIN outside acceptable range (1...24MHz)" #endif /** * @brief PLL output clock frequency. */ #define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE) /* PLL output frequency range check.*/ #if (STM32_PLLCLKOUT < 16000000) || (STM32_PLLCLKOUT > 24000000) #error "STM32_PLLCLKOUT outside acceptable range (16...24MHz)" #endif /** * @brief System clock source. */ #if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__) #define STM32_SYSCLK STM32_PLLCLKOUT #elif (STM32_SW == STM32_SW_HSI) #define STM32_SYSCLK STM32_HSICLK #elif (STM32_SW == STM32_SW_HSE) #define STM32_SYSCLK STM32_HSECLK #else #error "invalid STM32_SYSCLK_SW value specified" #endif /* Check on the system clock.*/ #if STM32_SYSCLK > 24000000 #error "STM32_SYSCLK above maximum rated frequency (24MHz)" #endif /** * @brief AHB frequency. */ #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) #define STM32_HCLK (STM32_SYSCLK / 1) #elif STM32_HPRE == STM32_HPRE_DIV2 #define STM32_HCLK (STM32_SYSCLK / 2) #elif STM32_HPRE == STM32_HPRE_DIV4 #define STM32_HCLK (STM32_SYSCLK / 4) #elif STM32_HPRE == STM32_HPRE_DIV8 #define STM32_HCLK (STM32_SYSCLK / 8) #elif STM32_HPRE == STM32_HPRE_DIV16 #define STM32_HCLK (STM32_SYSCLK / 16) #elif STM32_HPRE == STM32_HPRE_DIV64 #define STM32_HCLK (STM32_SYSCLK / 64) #elif STM32_HPRE == STM32_HPRE_DIV128 #define STM32_HCLK (STM32_SYSCLK / 128) #elif STM32_HPRE == STM32_HPRE_DIV256 #define STM32_HCLK (STM32_SYSCLK / 256) #elif STM32_HPRE == STM32_HPRE_DIV512 #define STM32_HCLK (STM32_SYSCLK / 512) #else #error "invalid STM32_HPRE value specified" #endif /* AHB frequency check.*/ #if STM32_HCLK > 24000000 #error "STM32_HCLK exceeding maximum frequency (24MHz)" #endif /** * @brief APB1 frequency. */ #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) #define STM32_PCLK1 (STM32_HCLK / 1) #elif STM32_PPRE1 == STM32_PPRE1_DIV2 #define STM32_PCLK1 (STM32_HCLK / 2) #elif STM32_PPRE1 == STM32_PPRE1_DIV4 #define STM32_PCLK1 (STM32_HCLK / 4) #elif STM32_PPRE1 == STM32_PPRE1_DIV8 #define STM32_PCLK1 (STM32_HCLK / 8) #elif STM32_PPRE1 == STM32_PPRE1_DIV16 #define STM32_PCLK1 (STM32_HCLK / 16) #else #error "invalid STM32_PPRE1 value specified" #endif /* APB1 frequency check.*/ #if STM32_PCLK2 > 24000000 #error "STM32_PCLK1 exceeding maximum frequency (24MHz)" #endif /** * @brief APB2 frequency. */ #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) #define STM32_PCLK2 (STM32_HCLK / 1) #elif STM32_PPRE2 == STM32_PPRE2_DIV2 #define STM32_PCLK2 (STM32_HCLK / 2) #elif STM32_PPRE2 == STM32_PPRE2_DIV4 #define STM32_PCLK2 (STM32_HCLK / 4) #elif STM32_PPRE2 == STM32_PPRE2_DIV8 #define STM32_PCLK2 (STM32_HCLK / 8) #elif STM32_PPRE2 == STM32_PPRE2_DIV16 #define STM32_PCLK2 (STM32_HCLK / 16) #else #error "invalid STM32_PPRE2 value specified" #endif /* APB2 frequency check.*/ #if STM32_PCLK2 > 24000000 #error "STM32_PCLK2 exceeding maximum frequency (24MHz)" #endif /** * @brief ADC frequency. */ #if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__) #define STM32_ADCCLK (STM32_PCLK2 / 2) #elif STM32_ADCPRE == STM32_ADCPRE_DIV4 #define STM32_ADCCLK (STM32_PCLK2 / 4) #elif STM32_ADCPRE == STM32_ADCPRE_DIV6 #define STM32_ADCCLK (STM32_PCLK2 / 6) #elif STM32_ADCPRE == STM32_ADCPRE_DIV8 #define STM32_ADCCLK (STM32_PCLK2 / 8) #else #error "invalid STM32_ADCPRE value specified" #endif /* ADC frequency check.*/ #if STM32_ADCCLK > 12000000 #error "STM32_ADCCLK exceeding maximum frequency (12MHz)" #endif /** * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. */ #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) #define STM32_TIMCLK1 (STM32_PCLK1 * 1) #else #define STM32_TIMCLK1 (STM32_PCLK1 * 2) #endif /** * @brief Timers 1, 8, 9, 10, 11 clock. */ #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) #define STM32_TIMCLK2 (STM32_PCLK2 * 1) #else #define STM32_TIMCLK2 (STM32_PCLK2 * 2) #endif /** * @brief Flash settings. */ #if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__) #define STM32_FLASHBITS 0x00000010 #elif STM32_HCLK <= 48000000 #define STM32_FLASHBITS 0x00000011 #else #define STM32_FLASHBITS 0x00000012 #endif #endif /* _HAL_LLD_F100_H_ */ /** @} */