/* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, 2011,2012 Giovanni Di Sirio. This file is part of ChibiOS/RT. ChibiOS/RT is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . */ /** * @file STM32/gpt_lld.h * @brief STM32 GPT subsystem low level driver header. * * @addtogroup GPT * @{ */ #ifndef _GPT_LLD_H_ #define _GPT_LLD_H_ #if HAL_USE_GPT || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ /** * @name Configuration options * @{ */ /** * @brief GPTD1 driver enable switch. * @details If set to @p TRUE the support for GPTD1 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM1 FALSE #endif /** * @brief GPTD2 driver enable switch. * @details If set to @p TRUE the support for GPTD2 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM2 FALSE #endif /** * @brief GPTD3 driver enable switch. * @details If set to @p TRUE the support for GPTD3 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM3 FALSE #endif /** * @brief GPTD4 driver enable switch. * @details If set to @p TRUE the support for GPTD4 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM4 FALSE #endif /** * @brief GPTD5 driver enable switch. * @details If set to @p TRUE the support for GPTD5 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM5 FALSE #endif /** * @brief GPTD8 driver enable switch. * @details If set to @p TRUE the support for GPTD8 is included. * @note The default is @p TRUE. */ #if !defined(STM32_GPT_USE_TIM8) || defined(__DOXYGEN__) #define STM32_GPT_USE_TIM8 FALSE #endif /** * @brief GPTD1 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM1_IRQ_PRIORITY 7 #endif /** * @brief GPTD2 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM2_IRQ_PRIORITY 7 #endif /** * @brief GPTD3 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM3_IRQ_PRIORITY 7 #endif /** * @brief GPTD4 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM4_IRQ_PRIORITY 7 #endif /** * @brief GPTD5 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM5_IRQ_PRIORITY 7 #endif /** * @brief GPTD5 interrupt priority level setting. */ #if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_GPT_TIM8_IRQ_PRIORITY 7 #endif /** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ #if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1 #error "TIM1 not present in the selected device" #endif #if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2 #error "TIM2 not present in the selected device" #endif #if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3 #error "TIM3 not present in the selected device" #endif #if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4 #error "TIM4 not present in the selected device" #endif #if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5 #error "TIM5 not present in the selected device" #endif #if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8 #error "TIM8 not present in the selected device" #endif #if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 && \ !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 && \ !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM8 #error "GPT driver activated but no TIM peripheral assigned" #endif #if STM32_GPT_USE_TIM1 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM1" #endif #if STM32_GPT_USE_TIM2 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM2" #endif #if STM32_GPT_USE_TIM3 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM3" #endif #if STM32_GPT_USE_TIM4 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM4" #endif #if STM32_GPT_USE_TIM5 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM5" #endif #if STM32_GPT_USE_TIM8 && \ !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TIM8" #endif /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ /** * @brief GPT frequency type. */ typedef uint32_t gptfreq_t; /** * @brief GPT counter type. */ typedef uint16_t gptcnt_t; /** * @brief Driver configuration structure. * @note It could be empty on some architectures. */ typedef struct { /** * @brief Timer clock in Hz. * @note The low level can use assertions in order to catch invalid * frequency specifications. */ gptfreq_t frequency; /** * @brief Timer callback pointer. * @note This callback is invoked on GPT counter events. */ gptcallback_t callback; /* End of the mandatory fields.*/ } GPTConfig; /** * @brief Structure representing a GPT driver. */ struct GPTDriver { /** * @brief Driver state. */ gptstate_t state; /** * @brief Current configuration data. */ const GPTConfig *config; #if defined(GPT_DRIVER_EXT_FIELDS) GPT_DRIVER_EXT_FIELDS #endif /* End of the mandatory fields.*/ /** * @brief Timer base clock. */ uint32_t clock; /** * @brief Pointer to the TIMx registers block. */ stm32_tim_t *tim; }; /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ #if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__) extern GPTDriver GPTD1; #endif #if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__) extern GPTDriver GPTD2; #endif #if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__) extern GPTDriver GPTD3; #endif #if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__) extern GPTDriver GPTD4; #endif #if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__) extern GPTDriver GPTD5; #endif #if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__) extern GPTDriver GPTD8; #endif #ifdef __cplusplus extern "C" { #endif void gpt_lld_init(void); void gpt_lld_start(GPTDriver *gptp); void gpt_lld_stop(GPTDriver *gptp); void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); void gpt_lld_stop_timer(GPTDriver *gptp); void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); #ifdef __cplusplus } #endif #endif /* HAL_USE_GPT */ #endif /* _GPT_LLD_H_ */ /** @} */