From 9487a1f58c40b5cc3bc98c0eb14dfd1a0c18b8c2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Oct 2018 15:32:45 +0000 Subject: OCTOSPI driver and demo, to be tested. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12395 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- testhal/STM32/multi/WSPI-MFS/.cproject | 37 ++++++++++++++++++++++++++++++++++ testhal/STM32/multi/WSPI-MFS/Makefile | 5 +++++ testhal/STM32/multi/WSPI-MFS/main.c | 13 +++++++++++- 3 files changed, 54 insertions(+), 1 deletion(-) (limited to 'testhal/STM32') diff --git a/testhal/STM32/multi/WSPI-MFS/.cproject b/testhal/STM32/multi/WSPI-MFS/.cproject index 5052dd0dd..23334856f 100644 --- a/testhal/STM32/multi/WSPI-MFS/.cproject +++ b/testhal/STM32/multi/WSPI-MFS/.cproject @@ -69,6 +69,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -78,6 +112,9 @@ + + + diff --git a/testhal/STM32/multi/WSPI-MFS/Makefile b/testhal/STM32/multi/WSPI-MFS/Makefile index 8fed918b3..0171204af 100644 --- a/testhal/STM32/multi/WSPI-MFS/Makefile +++ b/testhal/STM32/multi/WSPI-MFS/Makefile @@ -6,6 +6,9 @@ all: @echo @echo === Building for STM32L476-Discovery =============================== +@make --no-print-directory -f ./make/stm32l476_discovery.make all + @echo + @echo === Building for STM32L4R9-Discovery =============================== + +@make --no-print-directory -f ./make/stm32l4r9_discovery.make all @echo ==================================================================== @echo @@ -13,6 +16,8 @@ clean: @echo +@make --no-print-directory -f ./make/stm32l476_discovery.make clean @echo + +@make --no-print-directory -f ./make/stm32l4r9_discovery.make clean + @echo # ############################################################################## diff --git a/testhal/STM32/multi/WSPI-MFS/main.c b/testhal/STM32/multi/WSPI-MFS/main.c index 826daab70..0bce0c7f3 100644 --- a/testhal/STM32/multi/WSPI-MFS/main.c +++ b/testhal/STM32/multi/WSPI-MFS/main.c @@ -26,11 +26,22 @@ #include "portab.h" +#if defined(STM32_WSPI_USE_OCTOSPI1) /* 16MB device, 2 cycles delay after NCS.*/ const WSPIConfig WSPIcfg1 = { .end_cb = NULL, - .dcr = STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1) + .dcr1 = STM32_DCR1_DEVSIZE(24U) | STM32_DCR1_CSHT(1U), + .dcr2 = 0U, + .dcr3 = 0U, + .dcr4 = 0U }; +#else /* It is a quad SPI.*/ +/* 16MB device, 2 cycles delay after NCS.*/ +const WSPIConfig WSPIcfg1 = { + .end_cb = NULL, + .dcr = STM32_DCR_FSIZE(24U) | STM32_DCR_CSHT(1U) +}; +#endif const SNORConfig snorcfg1 = { .busp = &WSPID1, -- cgit v1.2.3