From beef652b8946a5fbf4245a0c3a07a411247614ad Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Oct 2018 16:52:55 +0000 Subject: Fixed a problem in L4+ PLLSAIx initialization, added options to mcuconf.h, updated mcuconf generator tool. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12397 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery') diff --git a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h index b8bbc1345..a54969cb4 100644 --- a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h +++ b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h @@ -69,11 +69,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK +#define STM32_PLLSAI1M_VALUE 1 #define STM32_PLLSAI1N_VALUE 72 #define STM32_PLLSAI1PDIV_VALUE 6 #define STM32_PLLSAI1P_VALUE 7 #define STM32_PLLSAI1Q_VALUE 6 #define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2M_VALUE 1 #define STM32_PLLSAI2N_VALUE 72 #define STM32_PLLSAI2PDIV_VALUE 6 #define STM32_PLLSAI2P_VALUE 7 -- cgit v1.2.3