From d5635adecc959228fefce27610f211087fefd87f Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Wed, 2 Jan 2019 11:43:13 +0000
Subject: Mass update of all drivers to use the new DMA API. What could
 possibly go wrong?

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12521 110e8d01-0319-4d1e-a829-52ad28d1bb01
---
 .../multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h  | 54 +++++++++++-----------
 1 file changed, 27 insertions(+), 27 deletions(-)

(limited to 'testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h')

diff --git a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
index a01ddd3f9..f8597eaae 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
  */
 #define STM32_ADC_COMPACT_SAMPLES           FALSE
 #define STM32_ADC_USE_ADC1                  FALSE
-#define STM32_ADC_ADC1_DMA_CHANNEL          10
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY
 #define STM32_ADC_ADC1_DMA_PRIORITY         2
 #define STM32_ADC_ADC12_IRQ_PRIORITY        5
 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5
@@ -150,8 +150,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      11
-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      12
+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
 
 /*
  * GPT driver system settings.
@@ -180,12 +180,12 @@
 #define STM32_I2C_USE_I2C2                  FALSE
 #define STM32_I2C_USE_I2C3                  FALSE
 #define STM32_I2C_BUSY_TIMEOUT              50
-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       6
-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       7
-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       8
-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       9
-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       8
-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       9
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
 #define STM32_I2C_I2C1_IRQ_PRIORITY         5
 #define STM32_I2C_I2C2_IRQ_PRIORITY         5
 #define STM32_I2C_I2C3_IRQ_PRIORITY         5
@@ -261,12 +261,12 @@
 #define STM32_SPI_USE_SPI1                  FALSE
 #define STM32_SPI_USE_SPI2                  FALSE
 #define STM32_SPI_USE_SPI3                  FALSE
-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       0
-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       1
-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       2
-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       3
-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       4
-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       5
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
 #define STM32_SPI_SPI1_DMA_PRIORITY         1
 #define STM32_SPI_SPI2_DMA_PRIORITY         1
 #define STM32_SPI_SPI3_DMA_PRIORITY         1
@@ -294,16 +294,16 @@
 #define STM32_UART_USE_USART3               FALSE
 #define STM32_UART_USE_UART4                FALSE
 #define STM32_UART_USE_UART5                FALSE
-#define STM32_UART_USART1_RX_DMA_CHANNEL    13
-#define STM32_UART_USART1_TX_DMA_CHANNEL    0
-#define STM32_UART_USART2_RX_DMA_CHANNEL    1
-#define STM32_UART_USART2_TX_DMA_CHANNEL    2
-#define STM32_UART_USART3_RX_DMA_CHANNEL    3
-#define STM32_UART_USART3_TX_DMA_CHANNEL    4
-#define STM32_UART_UART4_RX_DMA_CHANNEL     5
-#define STM32_UART_UART4_TX_DMA_CHANNEL     6
-#define STM32_UART_UART5_RX_DMA_CHANNEL     7
-#define STM32_UART_UART5_TX_DMA_CHANNEL     8
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
 #define STM32_UART_USART1_IRQ_PRIORITY      12
 #define STM32_UART_USART2_IRQ_PRIORITY      12
 #define STM32_UART_USART3_IRQ_PRIORITY      12
@@ -337,8 +337,8 @@
 #define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
 #define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10
 #define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10
-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9
-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10
+#define STM32_WSPI_OCTOSPI1_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
+#define STM32_WSPI_OCTOSPI2_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
 #define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1
 #define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1
 #define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
-- 
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