From 3a5c3788fa9bc4b900926daceb86ad525fb28df4 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Wed, 26 Aug 2015 12:42:52 +0000
Subject: Added cache handling example for F7 ADC and SPI demos.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8243 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 testhal/STM32/STM32F7xx/SPI/main.c | 91 +++++++++++++++++++++++++++++---------
 1 file changed, 70 insertions(+), 21 deletions(-)

(limited to 'testhal/STM32/STM32F7xx/SPI')

diff --git a/testhal/STM32/STM32F7xx/SPI/main.c b/testhal/STM32/STM32F7xx/SPI/main.c
index 996b3c9b7..cd7b3ed07 100644
--- a/testhal/STM32/STM32F7xx/SPI/main.c
+++ b/testhal/STM32/STM32F7xx/SPI/main.c
@@ -14,6 +14,8 @@
     limitations under the License.
 */
 
+#include <string.h>
+
 #include "ch.h"
 #include "hal.h"
 
@@ -21,6 +23,8 @@
 /* SPI driver related.                                                       */
 /*===========================================================================*/
 
+#define SPI_LOOPBACK
+
 /*
  * Maximum speed SPI configuration (27MHz, CPHA=0, CPOL=0, MSb first).
  */
@@ -45,9 +49,21 @@ static const SPIConfig ls_spicfg = {
 
 /*
  * SPI TX and RX buffers.
+ * Note, the buffer are aligned to a 32 bytes boundary because limitations
+ * imposed by the data cache. Note, this is GNU specific, it must be
+ * handled differently for other compilers.
  */
-static uint8_t txbuf[512];
-static uint8_t rxbuf[512];
+#define SPI_BUFFERS_SIZE    128U
+
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+static uint8_t txbuf[SPI_BUFFERS_SIZE];
+
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+static uint8_t rxbuf[SPI_BUFFERS_SIZE];
 
 /*===========================================================================*/
 /* Application code.                                                         */
@@ -62,14 +78,32 @@ static THD_FUNCTION(spi_thread_1, p) {
   (void)p;
   chRegSetThreadName("SPI thread 1");
   while (true) {
-    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
-    palSetPad(GPIOI, GPIOI_ARD_D13);    /* LED ON.                          */
-    spiStart(&SPID2, &hs_spicfg);       /* Setup transfer parameters.       */
-    spiSelect(&SPID2);                  /* Slave Select assertion.          */
-    spiExchange(&SPID2, 512,
-                txbuf, rxbuf);          /* Atomic transfer operations.      */
-    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
-    spiReleaseBus(&SPID2);              /* Ownership release.               */
+    unsigned i;
+
+    /* Bush acquisition and SPI reprogramming.*/
+    spiAcquireBus(&SPID2);
+    spiStart(&SPID2, &hs_spicfg);
+
+    /* Preparing data buffer and flushing cache.*/
+    for (i = 0; i < SPI_BUFFERS_SIZE; i++)
+      txbuf[i] = (uint8_t)i;
+    dmaBufferFlush(txbuf, txbuf + SPI_BUFFERS_SIZE);
+
+    /* Slave selection and data exchange.*/
+    spiSelect(&SPID2);
+    spiExchange(&SPID2, SPI_BUFFERS_SIZE, txbuf, rxbuf);
+    spiUnselect(&SPID2);
+
+#if defined(SPI_LOOPBACK)
+    /* Invalidating cache over the buffer then checking the
+       loopback result.*/
+    dmaBufferInvalidate(rxbuf, rxbuf + SPI_BUFFERS_SIZE);
+    if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
+      chSysHalt("loopback failure");
+#endif
+
+    /* Releasing the bus.*/
+    spiReleaseBus(&SPID2);
   }
 }
 
@@ -82,14 +116,32 @@ static THD_FUNCTION(spi_thread_2, p) {
   (void)p;
   chRegSetThreadName("SPI thread 2");
   while (true) {
-    spiAcquireBus(&SPID2);              /* Acquire ownership of the bus.    */
-    palClearPad(GPIOI, GPIOI_ARD_D13);  /* LED OFF.                         */
-    spiStart(&SPID2, &ls_spicfg);       /* Setup transfer parameters.       */
-    spiSelect(&SPID2);                  /* Slave Select assertion.          */
-    spiExchange(&SPID2, 512,
-                txbuf, rxbuf);          /* Atomic transfer operations.      */
-    spiUnselect(&SPID2);                /* Slave Select de-assertion.       */
-    spiReleaseBus(&SPID2);              /* Ownership release.               */
+    unsigned i;
+
+    /* Bush acquisition and SPI reprogramming.*/
+    spiAcquireBus(&SPID2);
+    spiStart(&SPID2, &ls_spicfg);
+
+    /* Preparing data buffer and flushing cache.*/
+    for (i = 0; i < SPI_BUFFERS_SIZE; i++)
+      txbuf[i] = (uint8_t)(128U + i);
+    dmaBufferFlush(txbuf, txbuf + SPI_BUFFERS_SIZE);
+
+    /* Slave selection and data exchange.*/
+    spiSelect(&SPID2);
+    spiExchange(&SPID2, SPI_BUFFERS_SIZE, txbuf, rxbuf);
+    spiUnselect(&SPID2);
+
+#if defined(SPI_LOOPBACK)
+    /* Invalidating cache over the buffer then checking the
+       loopback result.*/
+    dmaBufferInvalidate(rxbuf, rxbuf + SPI_BUFFERS_SIZE);
+    if (memcmp(txbuf, rxbuf, SPI_BUFFERS_SIZE) != 0)
+      chSysHalt("loopback failure");
+#endif
+
+    /* Releasing the bus.*/
+    spiReleaseBus(&SPID2);
   }
 }
 
@@ -97,7 +149,6 @@ static THD_FUNCTION(spi_thread_2, p) {
  * Application entry point.
  */
 int main(void) {
-  unsigned i;
 
   /*
    * System initializations.
@@ -136,8 +187,6 @@ int main(void) {
   /*
    * Prepare transmit pattern.
    */
-  for (i = 0; i < sizeof(txbuf); i++)
-    txbuf[i] = (uint8_t)i;
 
   /*
    * Starting the transmitter and receiver threads.
-- 
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