From 52cac10dbce9b24df71712ed15430387e57dd01e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 3 Jun 2013 14:40:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5804 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/SPC563Mxx/ADC/mcuconf.h | 29 +++++++++++++++++++++++++++++ testhal/SPC563Mxx/SPI/main.c | 5 ++--- testhal/SPC563Mxx/SPI/mcuconf.h | 28 ++++++++++++++++++++++------ 3 files changed, 53 insertions(+), 9 deletions(-) (limited to 'testhal/SPC563Mxx') diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index 43a7662ed..49ae96bab 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -82,3 +82,32 @@ #define SPC5_USE_ESCIB TRUE #define SPC5_ESCIA_PRIORITY 8 #define SPC5_ESCIB_PRIORITY 8 + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_USE_DSPI2 FALSE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_DMA_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DSPI2_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() diff --git a/testhal/SPC563Mxx/SPI/main.c b/testhal/SPC563Mxx/SPI/main.c index b71f85d78..25b67546b 100644 --- a/testhal/SPC563Mxx/SPI/main.c +++ b/testhal/SPC563Mxx/SPI/main.c @@ -24,10 +24,9 @@ static const SPIConfig hs_spicfg = { NULL, 0, 0, - SPC5_MCR_PCSIS0, /* MCR. */ SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ - SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ }; /* @@ -37,7 +36,6 @@ static const SPIConfig ls_spicfg = { NULL, 0, 0, - SPC5_MCR_PCSIS0, /* MCR. */ SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ @@ -119,6 +117,7 @@ int main(void) { SIU.PCR[103].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SIN */ SIU.PCR[104].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ SIU.PCR[105].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[0] */ + SIU.PCR[106].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* PCS[1] */ /* Testing sending and receiving at the same time.*/ spiExchange(&SPID2, 4, txbuf, rxbuf); diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h index 1b373d2cc..c96d6eea2 100644 --- a/testhal/SPC563Mxx/SPI/mcuconf.h +++ b/testhal/SPC563Mxx/SPI/mcuconf.h @@ -47,12 +47,12 @@ /* * ADC driver settings. */ -#define SPC5_ADC_USE_ADC0_Q0 TRUE -#define SPC5_ADC_USE_ADC0_Q1 TRUE -#define SPC5_ADC_USE_ADC0_Q2 TRUE -#define SPC5_ADC_USE_ADC1_Q3 TRUE -#define SPC5_ADC_USE_ADC1_Q4 TRUE -#define SPC5_ADC_USE_ADC1_Q5 TRUE +#define SPC5_ADC_USE_ADC0_Q0 FALSE +#define SPC5_ADC_USE_ADC0_Q1 FALSE +#define SPC5_ADC_USE_ADC0_Q2 FALSE +#define SPC5_ADC_USE_ADC1_Q3 FALSE +#define SPC5_ADC_USE_ADC1_Q4 FALSE +#define SPC5_ADC_USE_ADC1_Q5 FALSE #define SPC5_ADC_FIFO0_DMA_PRIO 12 #define SPC5_ADC_FIFO1_DMA_PRIO 12 #define SPC5_ADC_FIFO2_DMA_PRIO 12 @@ -88,6 +88,22 @@ */ #define SPC5_SPI_USE_DSPI1 TRUE #define SPC5_SPI_USE_DSPI2 TRUE +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) #define SPC5_SPI_DSPI1_DMA_PRIO 10 #define SPC5_SPI_DSPI2_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 -- cgit v1.2.3