From 126943984c591c952bd0b9f6b2d36d97be823de3 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 14 Jun 2013 12:34:59 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5848
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 testhal/SPC563Mxx/SPI/mcuconf.h | 29 +++++++++++++++++++++--------
 1 file changed, 21 insertions(+), 8 deletions(-)

(limited to 'testhal/SPC563Mxx/SPI')

diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h
index c96d6eea2..a06df4fdc 100644
--- a/testhal/SPC563Mxx/SPI/mcuconf.h
+++ b/testhal/SPC563Mxx/SPI/mcuconf.h
@@ -23,6 +23,8 @@
  *
  * IRQ priorities:
  * 1...15       Lowest...Highest.
+ * DMA priorities:
+ * 0...15       Highest...Lowest.
  */
 
 #define SPC563Mxx_MCUCONF
@@ -44,6 +46,25 @@
                                              BIUCR_PFLIM_ON_MISS |          \
                                              BIUCR_BFEN)
 
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \
+                                             EDMA_CR_GRP2PRI(2) |           \
+                                             EDMA_CR_GRP1PRI(1) |           \
+                                             EDMA_CR_GRP0PRI(0) |           \
+                                             EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP1_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP2_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_GROUP3_PRIORITIES                                         \
+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define SPC5_EDMA_ERROR_IRQ_PRIO            2
+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()
+
 /*
  * ADC driver settings.
  */
@@ -53,12 +74,6 @@
 #define SPC5_ADC_USE_ADC1_Q3                FALSE
 #define SPC5_ADC_USE_ADC1_Q4                FALSE
 #define SPC5_ADC_USE_ADC1_Q5                FALSE
-#define SPC5_ADC_FIFO0_DMA_PRIO             12
-#define SPC5_ADC_FIFO1_DMA_PRIO             12
-#define SPC5_ADC_FIFO2_DMA_PRIO             12
-#define SPC5_ADC_FIFO3_DMA_PRIO             12
-#define SPC5_ADC_FIFO4_DMA_PRIO             12
-#define SPC5_ADC_FIFO5_DMA_PRIO             12
 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12
 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12
@@ -104,8 +119,6 @@
                                              SPC5_MCR_PCSIS5 |              \
                                              SPC5_MCR_PCSIS6 |              \
                                              SPC5_MCR_PCSIS7)
-#define SPC5_SPI_DSPI1_DMA_PRIO             10
-#define SPC5_SPI_DSPI2_DMA_PRIO             10
 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10
 #define SPC5_SPI_DSPI1_IRQ_PRIO             10
-- 
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