From d12b4ee2529f93c3320921593284b18acf0f4cd2 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 26 Aug 2014 08:18:49 +0000
Subject: [FSMC NAND] Low level driver cosmetical cleanup

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7194 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c | 18 ++++++---------
 os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h | 38 +++++++++++++-------------------
 2 files changed, 22 insertions(+), 34 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
index d0cf573dc..3739e88eb 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
@@ -20,7 +20,7 @@
 
 /**
  * @file    nand_lld.c
- * @brief   NAND Driver subsystem low level driver source template.
+ * @brief   NAND Driver subsystem low level driver source.
  *
  * @addtogroup NAND
  * @{
@@ -252,7 +252,7 @@ void nand_lld_init(void) {
   NANDD1.datalen  = 0;
   NANDD1.thread   = NULL;
   NANDD1.dma      = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
-  NANDD1.nand     = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE;
+  NANDD1.nand     = FSMCD1.nand1;
   NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA;
   NANDD1.map_cmd  = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD;
   NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR;
@@ -265,7 +265,7 @@ void nand_lld_init(void) {
   NANDD2.datalen  = 0;
   NANDD2.thread   = NULL;
   NANDD2.dma      = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM);
-  NANDD2.nand     = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE;
+  NANDD2.nand     = FSMCD1.nand2;
   NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA;
   NANDD2.map_cmd  = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD;
   NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR;
@@ -403,8 +403,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
     nandp->nand->PCR |= FSMC_PCR_ECCEN;
   }
 
-  dmaStartMemCopy(nandp->dma, nandp->dmamode,
-                           data, nandp->map_data, datalen);
+  dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, datalen);
 
   nand_lld_suspend_thread(nandp);
   osalSysUnlock();
@@ -430,8 +429,7 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data,
  *
  * @notapi
  */
-uint8_t nand_lld_erase(NANDDriver *nandp,
-                                        uint8_t *addr, size_t addrlen){
+uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen){
 
   nandp->state = NAND_ERASE;
 
@@ -457,8 +455,7 @@ uint8_t nand_lld_erase(NANDDriver *nandp,
  *
  * @notapi
  */
-void nand_lld_polled_read_data(NANDDriver *nandp,
-                                                  uint8_t *data, size_t len){
+void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len){
   size_t i = 0;
 
   for (i=0; i<len; i++)
@@ -474,8 +471,7 @@ void nand_lld_polled_read_data(NANDDriver *nandp,
  *
  * @notapi
  */
-void nand_lld_write_addr(NANDDriver *nandp,
-                                            const uint8_t *addr, size_t len){
+void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len){
   size_t i = 0;
 
   for (i=0; i<len; i++)
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
index 6222caa3f..618255fd7 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h
@@ -20,7 +20,7 @@
 
 /**
  * @file    nand_lld.h
- * @brief   NAND Driver subsystem low level driver header template.
+ * @brief   NAND Driver subsystem low level driver header.
  *
  * @addtogroup NAND
  * @{
@@ -38,7 +38,6 @@
 /*===========================================================================*/
 #define NAND_MIN_PAGE_SIZE       256
 #define NAND_MAX_PAGE_SIZE       8192
-#define NAND_BAD_MAP_END_MARK    ((uint16_t)0xFFFF)
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -49,10 +48,10 @@
  * @{
  */
 /**
- * @brief   EMD FSMC1 interrupt priority level setting.
+ * @brief   FSMC1 interrupt priority level setting.
  */
 #if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EMC_FSMC1_IRQ_PRIORITY                10
+#define STM32_EMC_FSMC1_IRQ_PRIORITY      10
 #endif
 
 /**
@@ -60,7 +59,7 @@
  * @details If set to @p TRUE the support for NAND1 is included.
  */
 #if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_NAND1                  FALSE
+#define STM32_NAND_USE_NAND1              FALSE
 #endif
 
 /**
@@ -68,7 +67,7 @@
  * @details If set to @p TRUE the support for NAND2 is included.
  */
 #if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_NAND2                  FALSE
+#define STM32_NAND_USE_NAND2              FALSE
 #endif
 
 /**
@@ -77,7 +76,7 @@
  *          error can only happen because programming errors.
  */
 #if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define STM32_NAND_DMA_ERROR_HOOK(nandp)      osalSysHalt("DMA failure")
+#define STM32_NAND_DMA_ERROR_HOOK(nandp)  osalSysHalt("DMA failure")
 #endif
 
 /**
@@ -85,29 +84,29 @@
  * @details If set to @p TRUE the support for internal FSMC interrupt included.
  */
 #if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__)
-#define STM32_NAND_USE_INT                       FALSE
+#define STM32_NAND_USE_INT                FALSE
 #endif
 
 /**
 * @brief   NAND1 DMA priority (0..3|lowest..highest).
 */
 #if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_NAND_NAND1_DMA_PRIORITY         0
+#define STM32_NAND_NAND1_DMA_PRIORITY     0
 #endif
 
 /**
 * @brief   NAND2 DMA priority (0..3|lowest..highest).
 */
 #if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_NAND_NAND2_DMA_PRIORITY         0
+#define STM32_NAND_NAND2_DMA_PRIORITY     0
 #endif
 
 /**
- * @brief   DMA stream used for NAND1 operations.
+ * @brief   DMA stream used for NAND operations.
  * @note    This option is only available on platforms with enhanced DMA.
  */
 #if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_NAND_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)
+#define STM32_NAND_DMA_STREAM             STM32_DMA_STREAM_ID(2, 6)
 #endif
 
 /** @} */
@@ -120,11 +119,7 @@
 #error "NAND driver activated but no NAND peripheral assigned"
 #endif
 
-#if STM32_NAND_USE_FSMC_NAND1 && !STM32_HAS_FSMC
-#error "FSMC not present in the selected device"
-#endif
-
-#if STM32_NAND_USE_FSMC_NAND2 && !STM32_HAS_FSMC
+#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC
 #error "FSMC not present in the selected device"
 #endif
 
@@ -324,12 +319,9 @@ extern "C" {
           size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
   void nand_lld_read_data(NANDDriver *nandp, uint8_t *data,
           size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc);
-  void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data,
-          size_t len);
-  uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr,
-          size_t addrlen);
-  void nand_lld_write_addr(NANDDriver *nandp,
-          const uint8_t *addr, size_t len);
+  void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len);
+  uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen);
+  void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len);
   void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd);
   uint8_t nand_lld_read_status(NANDDriver *nandp);
 #ifdef __cplusplus
-- 
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