From cfdf3905dbd6af629d40096940fb2845c6ca6668 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Apr 2010 12:37:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1867 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/GCC/ARMCMx/chcore_v7m_test.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) (limited to 'os') diff --git a/os/ports/GCC/ARMCMx/chcore_v7m_test.c b/os/ports/GCC/ARMCMx/chcore_v7m_test.c index 4df46f065..09e683f00 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m_test.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m_test.c @@ -27,6 +27,22 @@ #include "ch.h" +/** + * @brief Internal context stacking. + */ +#define PUSH_CONTEXT(sp) { \ + asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \ +} + + +/** + * @brief Internal context unstacking. + */ +#define POP_CONTEXT(sp) { \ + asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ + : : "r" (sp)); \ +} + #if !CH_OPTIMIZE_SPEED void _port_lock(void) { register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; @@ -87,8 +103,11 @@ void _port_irq_epilogue(void) { asm volatile ("msr PSP, %0" : : "r" (ctxp)); ctxp->pc = _port_switch_from_isr; ctxp->xpsr = (regarm_t)0x01000000; + /* Note, returning without unlocking is intentional, this is done in + order to keep the rest of the context switching atomic.*/ return; } + /* ISR exit without context switching.*/ port_unlock_from_isr(); } @@ -105,15 +124,6 @@ void _port_switch_from_isr(void) { asm volatile ("svc #0"); } -#define PUSH_CONTEXT(sp) { \ - asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ - : : "r" (sp)); \ -} - /** * @brief Performs a context switch between two threads. * @details This is the most critical code in any port, this function -- cgit v1.2.3