From b54cc0d618dbf54b384ad88897489c45c94e6692 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Mar 2014 10:57:40 +0000 Subject: Fixed bug #474. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6784 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F30x/hal_lld.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'os') diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h index 97e564724..eb046a7b7 100644 --- a/os/hal/ports/STM32/STM32F30x/hal_lld.h +++ b/os/hal/ports/STM32/STM32F30x/hal_lld.h @@ -214,20 +214,20 @@ #define STM32_ADC12PRES_DIV64 (25 << 4) /**< ADC12 clock is PLL/64. */ #define STM32_ADC12PRES_DIV128 (26 << 4) /**< ADC12 clock is PLL/128. */ #define STM32_ADC12PRES_DIV256 (27 << 4) /**< ADC12 clock is PLL/256. */ -#define STM32_ADC34PRES_MASK (31 << 4) /**< ADC34 clock source mask. */ -#define STM32_ADC34PRES_NOCLOCK (0 << 4) /**< ADC34 clock is disabled. */ -#define STM32_ADC34PRES_DIV1 (16 << 4) /**< ADC34 clock is PLL/1. */ -#define STM32_ADC34PRES_DIV2 (17 << 4) /**< ADC34 clock is PLL/2. */ -#define STM32_ADC34PRES_DIV4 (18 << 4) /**< ADC34 clock is PLL/4. */ -#define STM32_ADC34PRES_DIV6 (19 << 4) /**< ADC34 clock is PLL/6. */ -#define STM32_ADC34PRES_DIV8 (20 << 4) /**< ADC34 clock is PLL/8. */ -#define STM32_ADC34PRES_DIV10 (21 << 4) /**< ADC34 clock is PLL/10. */ -#define STM32_ADC34PRES_DIV12 (22 << 4) /**< ADC34 clock is PLL/12. */ -#define STM32_ADC34PRES_DIV16 (23 << 4) /**< ADC34 clock is PLL/16. */ -#define STM32_ADC34PRES_DIV32 (24 << 4) /**< ADC34 clock is PLL/32. */ -#define STM32_ADC34PRES_DIV64 (25 << 4) /**< ADC34 clock is PLL/64. */ -#define STM32_ADC34PRES_DIV128 (26 << 4) /**< ADC34 clock is PLL/128. */ -#define STM32_ADC34PRES_DIV256 (27 << 4) /**< ADC34 clock is PLL/256. */ +#define STM32_ADC34PRES_MASK (31 << 9) /**< ADC34 clock source mask. */ +#define STM32_ADC34PRES_NOCLOCK (0 << 9) /**< ADC34 clock is disabled. */ +#define STM32_ADC34PRES_DIV1 (16 << 9) /**< ADC34 clock is PLL/1. */ +#define STM32_ADC34PRES_DIV2 (17 << 9) /**< ADC34 clock is PLL/2. */ +#define STM32_ADC34PRES_DIV4 (18 << 9) /**< ADC34 clock is PLL/4. */ +#define STM32_ADC34PRES_DIV6 (19 << 9) /**< ADC34 clock is PLL/6. */ +#define STM32_ADC34PRES_DIV8 (20 << 9) /**< ADC34 clock is PLL/8. */ +#define STM32_ADC34PRES_DIV10 (21 << 9) /**< ADC34 clock is PLL/10. */ +#define STM32_ADC34PRES_DIV12 (22 << 9) /**< ADC34 clock is PLL/12. */ +#define STM32_ADC34PRES_DIV16 (23 << 9) /**< ADC34 clock is PLL/16. */ +#define STM32_ADC34PRES_DIV32 (24 << 9) /**< ADC34 clock is PLL/32. */ +#define STM32_ADC34PRES_DIV64 (25 << 9) /**< ADC34 clock is PLL/64. */ +#define STM32_ADC34PRES_DIV128 (26 << 9) /**< ADC34 clock is PLL/128. */ +#define STM32_ADC34PRES_DIV256 (27 << 9) /**< ADC34 clock is PLL/256. */ /** @} */ /** -- cgit v1.2.3