From a59a43bc288b159a32cd994b5dadb883cfa234ae Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 13 Aug 2015 10:04:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8211 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F7xx/hal_lld.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'os') diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 4144cab73..1c2c2e364 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -133,13 +133,15 @@ void hal_lld_init(void) { /* If the DMA is in use then the DMA-accessible RAM must be programmed as Write Through using the MPU, region zero is used with a size of 512kB, the sub-regions are programmed as follow: - - 0..4, enabled, it is the normal, DMA-accessible, RAM. + - 0,, disabled, it is the normal the DTCM RAM. + - 1..4, enabled, it is the normal, DMA-accessible, RAM. - 5..7, disabled, beyond RAM area. The system memory layout is used as "background" for the MPU regions.*/ mpuConfigureRegion(MPU_REGION_0, 0x20000000U, MPU_RASR_ATTR_AP_RW_RW | MPU_RASR_ATTR_CACHEABLE_WT_NWA | + MPU_RNR_REGION(1) | MPU_RNR_REGION(5) | MPU_RNR_REGION(6) | MPU_RNR_REGION(7) | -- cgit v1.2.3