From 98e42289275e60e582d8bbf080ea356d306ef8e9 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 28 Jun 2016 11:45:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9674 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/startup/e200/devices/SPC560BCxx/boot.S | 214 +++++++++++ os/common/startup/e200/devices/SPC560BCxx/boot.s | 214 ----------- os/common/startup/e200/devices/SPC560Bxx/boot.S | 214 +++++++++++ os/common/startup/e200/devices/SPC560Bxx/boot.s | 214 ----------- os/common/startup/e200/devices/SPC560Dxx/boot.S | 214 +++++++++++ os/common/startup/e200/devices/SPC560Dxx/boot.s | 214 ----------- os/common/startup/e200/devices/SPC560Pxx/boot.S | 214 +++++++++++ os/common/startup/e200/devices/SPC560Pxx/boot.s | 214 ----------- os/common/startup/e200/devices/SPC563Mxx/boot.S | 188 ++++++++++ os/common/startup/e200/devices/SPC563Mxx/boot.s | 188 ---------- os/common/startup/e200/devices/SPC564Axx/boot.S | 353 ++++++++++++++++++ os/common/startup/e200/devices/SPC564Axx/boot.s | 353 ------------------ os/common/startup/e200/devices/SPC56ECxx/boot.S | 403 ++++++++++++++++++++ os/common/startup/e200/devices/SPC56ECxx/boot.s | 403 -------------------- os/common/startup/e200/devices/SPC56ELxx/boot.S | 405 +++++++++++++++++++++ os/common/startup/e200/devices/SPC56ELxx/boot.s | 405 --------------------- .../startup/e200/devices/SPC57EMxx_HSM/boot.h | 93 ----- .../startup/e200/devices/SPC57EMxx_HSM/boot.s | 208 ----------- .../startup/e200/devices/SPC57EMxx_HSM/intc.h | 94 ----- .../startup/e200/devices/SPC57EMxx_HSM/ppcparams.h | 88 ----- 20 files changed, 2205 insertions(+), 2688 deletions(-) create mode 100644 os/common/startup/e200/devices/SPC560BCxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC560BCxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC560Bxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC560Bxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC560Dxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC560Dxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC560Pxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC560Pxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC563Mxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC563Mxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC564Axx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC564Axx/boot.s create mode 100644 os/common/startup/e200/devices/SPC56ECxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC56ECxx/boot.s create mode 100644 os/common/startup/e200/devices/SPC56ELxx/boot.S delete mode 100644 os/common/startup/e200/devices/SPC56ELxx/boot.s delete mode 100644 os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h delete mode 100644 os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s delete mode 100644 os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h delete mode 100644 os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h (limited to 'os') diff --git a/os/common/startup/e200/devices/SPC560BCxx/boot.S b/os/common/startup/e200/devices/SPC560BCxx/boot.S new file mode 100644 index 000000000..f7a99c2d7 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560BCxx/boot.S @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/boot.s + * @brief SPC560BCxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: + b _IVOR0 + .align 4 + b _IVOR1 + .align 4 + b _IVOR2 + .align 4 + b _IVOR3 + .align 4 + b _IVOR4 + .align 4 + b _IVOR5 + .align 4 + b _IVOR6 + .align 4 + b _IVOR7 + .align 4 + b _IVOR8 + .align 4 + b _IVOR9 + .align 4 + b _IVOR10 + .align 4 + b _IVOR11 + .align 4 + b _IVOR12 + .align 4 + b _IVOR13 + .align 4 + b _IVOR14 + .align 4 + b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC560BCxx/boot.s b/os/common/startup/e200/devices/SPC560BCxx/boot.s deleted file mode 100644 index f7a99c2d7..000000000 --- a/os/common/startup/e200/devices/SPC560BCxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560BCxx/boot.s - * @brief SPC560BCxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Bxx/boot.S b/os/common/startup/e200/devices/SPC560Bxx/boot.S new file mode 100644 index 000000000..46af60294 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Bxx/boot.S @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Bxx/boot.s + * @brief SPC560Bxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: + b _IVOR0 + .align 4 + b _IVOR1 + .align 4 + b _IVOR2 + .align 4 + b _IVOR3 + .align 4 + b _IVOR4 + .align 4 + b _IVOR5 + .align 4 + b _IVOR6 + .align 4 + b _IVOR7 + .align 4 + b _IVOR8 + .align 4 + b _IVOR9 + .align 4 + b _IVOR10 + .align 4 + b _IVOR11 + .align 4 + b _IVOR12 + .align 4 + b _IVOR13 + .align 4 + b _IVOR14 + .align 4 + b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Bxx/boot.s b/os/common/startup/e200/devices/SPC560Bxx/boot.s deleted file mode 100644 index 46af60294..000000000 --- a/os/common/startup/e200/devices/SPC560Bxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Bxx/boot.s - * @brief SPC560Bxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Dxx/boot.S b/os/common/startup/e200/devices/SPC560Dxx/boot.S new file mode 100644 index 000000000..0c056f3f2 --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Dxx/boot.S @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/boot.s + * @brief SPC560Dxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis r4, __ram_reloc_start__@h + ori r4, r4, __ram_reloc_start__@l + lis r5, __ram_reloc_dest__@h + ori r5, r5, __ram_reloc_dest__@l + lis r6, __ram_reloc_end__@h + ori r6, r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, r4, r6 + bge cr0, .relend + lwz r7, 0(r4) + addi r4, r4, 4 + stw r7, 0(r5) + addi r5, r5, 4 + b .relloop +.relend: + lis r3, _boot_address@h + ori r3, r3, _boot_address@l + mtctr r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor r0, r0, r0 + xor r1, r1, r1 + xor r2, r2, r2 + xor r3, r3, r3 + xor r4, r4, r4 + xor r5, r5, r5 + xor r6, r6, r6 + xor r7, r7, r7 + xor r8, r8, r8 + xor r9, r9, r9 + xor r10, r10, r10 + xor r11, r11, r11 + xor r12, r12, r12 + xor r13, r13, r13 + xor r14, r14, r14 + xor r15, r15, r15 + xor r16, r16, r16 + xor r17, r17, r17 + xor r18, r18, r18 + xor r19, r19, r19 + xor r20, r20, r20 + xor r21, r21, r21 + xor r22, r22, r22 + xor r23, r23, r23 + xor r24, r24, r24 + xor r25, r25, r25 + xor r26, r26, r26 + xor r27, r27, r27 + xor r28, r28, r28 + xor r29, r29, r29 + xor r30, r30, r30 + xor r31, r31, r31 + lis r4, __ram_start__@h + ori r4, r4, __ram_start__@l + lis r5, __ram_end__@h + ori r5, r5, __ram_end__@l +.cleareccloop: + cmpl cr0, r4, r5 + bge cr0, .cleareccend + stmw r16, 0(r4) + addi r4, r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li r3, BOOT_BUCSR_DEFAULT + mtspr 1013, r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis r3, BOOT_MSR_DEFAULT@h + ori r3, r3, BOOT_MSR_DEFAULT@l + mtMSR r3 + + /* IVPR initialization.*/ + lis r3, __ivpr_base__@h + ori r3, r3, __ivpr_base__@l + mtIVPR r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: + b _IVOR0 + .align 4 + b _IVOR1 + .align 4 + b _IVOR2 + .align 4 + b _IVOR3 + .align 4 + b _IVOR4 + .align 4 + b _IVOR5 + .align 4 + b _IVOR6 + .align 4 + b _IVOR7 + .align 4 + b _IVOR8 + .align 4 + b _IVOR9 + .align 4 + b _IVOR10 + .align 4 + b _IVOR11 + .align 4 + b _IVOR12 + .align 4 + b _IVOR13 + .align 4 + b _IVOR14 + .align 4 + b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Dxx/boot.s b/os/common/startup/e200/devices/SPC560Dxx/boot.s deleted file mode 100644 index 0c056f3f2..000000000 --- a/os/common/startup/e200/devices/SPC560Dxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Dxx/boot.s - * @brief SPC560Dxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis r4, __ram_reloc_start__@h - ori r4, r4, __ram_reloc_start__@l - lis r5, __ram_reloc_dest__@h - ori r5, r5, __ram_reloc_dest__@l - lis r6, __ram_reloc_end__@h - ori r6, r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, r4, r6 - bge cr0, .relend - lwz r7, 0(r4) - addi r4, r4, 4 - stw r7, 0(r5) - addi r5, r5, 4 - b .relloop -.relend: - lis r3, _boot_address@h - ori r3, r3, _boot_address@l - mtctr r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor r0, r0, r0 - xor r1, r1, r1 - xor r2, r2, r2 - xor r3, r3, r3 - xor r4, r4, r4 - xor r5, r5, r5 - xor r6, r6, r6 - xor r7, r7, r7 - xor r8, r8, r8 - xor r9, r9, r9 - xor r10, r10, r10 - xor r11, r11, r11 - xor r12, r12, r12 - xor r13, r13, r13 - xor r14, r14, r14 - xor r15, r15, r15 - xor r16, r16, r16 - xor r17, r17, r17 - xor r18, r18, r18 - xor r19, r19, r19 - xor r20, r20, r20 - xor r21, r21, r21 - xor r22, r22, r22 - xor r23, r23, r23 - xor r24, r24, r24 - xor r25, r25, r25 - xor r26, r26, r26 - xor r27, r27, r27 - xor r28, r28, r28 - xor r29, r29, r29 - xor r30, r30, r30 - xor r31, r31, r31 - lis r4, __ram_start__@h - ori r4, r4, __ram_start__@l - lis r5, __ram_end__@h - ori r5, r5, __ram_end__@l -.cleareccloop: - cmpl cr0, r4, r5 - bge cr0, .cleareccend - stmw r16, 0(r4) - addi r4, r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li r3, BOOT_BUCSR_DEFAULT - mtspr 1013, r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis r3, BOOT_MSR_DEFAULT@h - ori r3, r3, BOOT_MSR_DEFAULT@l - mtMSR r3 - - /* IVPR initialization.*/ - lis r3, __ivpr_base__@h - ori r3, r3, __ivpr_base__@l - mtIVPR r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Pxx/boot.S b/os/common/startup/e200/devices/SPC560Pxx/boot.S new file mode 100644 index 000000000..81b34158c --- /dev/null +++ b/os/common/startup/e200/devices/SPC560Pxx/boot.S @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Pxx/boot.s + * @brief SPC560Pxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: + b _IVOR0 + .align 4 + b _IVOR1 + .align 4 + b _IVOR2 + .align 4 + b _IVOR3 + .align 4 + b _IVOR4 + .align 4 + b _IVOR5 + .align 4 + b _IVOR6 + .align 4 + b _IVOR7 + .align 4 + b _IVOR8 + .align 4 + b _IVOR9 + .align 4 + b _IVOR10 + .align 4 + b _IVOR11 + .align 4 + b _IVOR12 + .align 4 + b _IVOR13 + .align 4 + b _IVOR14 + .align 4 + b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: + .global _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC560Pxx/boot.s b/os/common/startup/e200/devices/SPC560Pxx/boot.s deleted file mode 100644 index 81b34158c..000000000 --- a/os/common/startup/e200/devices/SPC560Pxx/boot.s +++ /dev/null @@ -1,214 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC560Pxx/boot.s - * @brief SPC560Pxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - - .long 0x015A0000 - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: - b _IVOR0 - .align 4 - b _IVOR1 - .align 4 - b _IVOR2 - .align 4 - b _IVOR3 - .align 4 - b _IVOR4 - .align 4 - b _IVOR5 - .align 4 - b _IVOR6 - .align 4 - b _IVOR7 - .align 4 - b _IVOR8 - .align 4 - b _IVOR9 - .align 4 - b _IVOR10 - .align 4 - b _IVOR11 - .align 4 - b _IVOR12 - .align 4 - b _IVOR13 - .align 4 - b _IVOR14 - .align 4 - b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC563Mxx/boot.S b/os/common/startup/e200/devices/SPC563Mxx/boot.S new file mode 100644 index 000000000..1ba1b728d --- /dev/null +++ b/os/common/startup/e200/devices/SPC563Mxx/boot.S @@ -0,0 +1,188 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/boot.s + * @brief SPC563Mxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC563Mxx/boot.s b/os/common/startup/e200/devices/SPC563Mxx/boot.s deleted file mode 100644 index 1ba1b728d..000000000 --- a/os/common/startup/e200/devices/SPC563Mxx/boot.s +++ /dev/null @@ -1,188 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC563Mxx/boot.s - * @brief SPC563Mxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_coreinit: - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC564Axx/boot.S b/os/common/startup/e200/devices/SPC564Axx/boot.S new file mode 100644 index 000000000..76c2b57ff --- /dev/null +++ b/os/common/startup/e200/devices/SPC564Axx/boot.S @@ -0,0 +1,353 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/boot.s + * @brief SPC564Axx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 +_coreinit: + /* + * Invalidating all TLBs except TLB1. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB0 allocated to internal RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * *Finally* the TLB1 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC564Axx/boot.s b/os/common/startup/e200/devices/SPC564Axx/boot.s deleted file mode 100644 index 76c2b57ff..000000000 --- a/os/common/startup/e200/devices/SPC564Axx/boot.s +++ /dev/null @@ -1,353 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC564Axx/boot.s - * @brief SPC564Axx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr - - .align 2 -_coreinit: - /* - * Invalidating all TLBs except TLB1. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB0 allocated to internal RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * *Finally* the TLB1 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC56ECxx/boot.S b/os/common/startup/e200/devices/SPC56ECxx/boot.S new file mode 100644 index 000000000..f6ba0b07d --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ECxx/boot.S @@ -0,0 +1,403 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ECxx/boot.s + * @brief SPC56ECxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 +_coreinit: + /* + * Invalidating all TLBs except TLB0. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB1 allocated to internal RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB5 allocated to on-platform peripherals. + */ + lis %r3, TLB5_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB5_MAS1@h + ori %r3, %r3, TLB5_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB5_MAS2@h + ori %r3, %r3, TLB5_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB5_MAS3@h + ori %r3, %r3, TLB5_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Special function registers clearing, required in order to avoid + * possible problems with lockstep mode. + */ + mtcrf 0xFF, %r31 + mtspr 9, %r31 /* CTR */ + mtspr 22, %r31 /* DEC */ + mtspr 26, %r31 /* SRR0-1 */ + mtspr 27, %r31 + mtspr 54, %r31 /* DECAR */ + mtspr 58, %r31 /* CSRR0-1 */ + mtspr 59, %r31 + mtspr 61, %r31 /* DEAR */ + mtspr 256, %r31 /* USPRG0 */ + mtspr 272, %r31 /* SPRG1-7 */ + mtspr 273, %r31 + mtspr 274, %r31 + mtspr 275, %r31 + mtspr 276, %r31 + mtspr 277, %r31 + mtspr 278, %r31 + mtspr 279, %r31 + mtspr 285, %r31 /* TBU */ + mtspr 284, %r31 /* TBL */ +#if 0 + mtspr 318, %r31 /* DVC1-2 */ + mtspr 319, %r31 +#endif + mtspr 562, %r31 /* DBCNT */ + mtspr 570, %r31 /* MCSRR0 */ + mtspr 571, %r31 /* MCSRR1 */ + mtspr 604, %r31 /* SPRG8-9 */ + mtspr 605, %r31 + + /* + * *Finally* the TLB0 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC56ECxx/boot.s b/os/common/startup/e200/devices/SPC56ECxx/boot.s deleted file mode 100644 index f6ba0b07d..000000000 --- a/os/common/startup/e200/devices/SPC56ECxx/boot.s +++ /dev/null @@ -1,403 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ECxx/boot.s - * @brief SPC56ECxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: -#if BOOT_PERFORM_CORE_INIT - bl _coreinit -#endif - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr - - .align 2 -_coreinit: - /* - * Invalidating all TLBs except TLB0. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB1 allocated to internal RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB5 allocated to on-platform peripherals. - */ - lis %r3, TLB5_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB5_MAS1@h - ori %r3, %r3, TLB5_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB5_MAS2@h - ori %r3, %r3, TLB5_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB5_MAS3@h - ori %r3, %r3, TLB5_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Special function registers clearing, required in order to avoid - * possible problems with lockstep mode. - */ - mtcrf 0xFF, %r31 - mtspr 9, %r31 /* CTR */ - mtspr 22, %r31 /* DEC */ - mtspr 26, %r31 /* SRR0-1 */ - mtspr 27, %r31 - mtspr 54, %r31 /* DECAR */ - mtspr 58, %r31 /* CSRR0-1 */ - mtspr 59, %r31 - mtspr 61, %r31 /* DEAR */ - mtspr 256, %r31 /* USPRG0 */ - mtspr 272, %r31 /* SPRG1-7 */ - mtspr 273, %r31 - mtspr 274, %r31 - mtspr 275, %r31 - mtspr 276, %r31 - mtspr 277, %r31 - mtspr 278, %r31 - mtspr 279, %r31 - mtspr 285, %r31 /* TBU */ - mtspr 284, %r31 /* TBL */ -#if 0 - mtspr 318, %r31 /* DVC1-2 */ - mtspr 319, %r31 -#endif - mtspr 562, %r31 /* DBCNT */ - mtspr 570, %r31 /* MCSRR0 */ - mtspr 571, %r31 /* MCSRR1 */ - mtspr 604, %r31 /* SPRG8-9 */ - mtspr 605, %r31 - - /* - * *Finally* the TLB0 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC56ELxx/boot.S b/os/common/startup/e200/devices/SPC56ELxx/boot.S new file mode 100644 index 000000000..9446823e5 --- /dev/null +++ b/os/common/startup/e200/devices/SPC56ELxx/boot.S @@ -0,0 +1,405 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC56ELxx/boot.s + * @brief SPC56ELxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: + bl _coreinit + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + isync + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + .align 2 +_coreinit: +#if BOOT_PERFORM_CORE_INIT + /* + * Invalidating all TLBs except TLB0. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB1 allocated to internal RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB5 allocated to on-platform peripherals. + */ + lis %r3, TLB5_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB5_MAS1@h + ori %r3, %r3, TLB5_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB5_MAS2@h + ori %r3, %r3, TLB5_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB5_MAS3@h + ori %r3, %r3, TLB5_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Special function registers clearing, required in order to avoid + * possible problems with lockstep mode. + */ + mtcrf 0xFF, %r31 + mtspr 9, %r31 /* CTR */ + mtspr 22, %r31 /* DEC */ + mtspr 26, %r31 /* SRR0-1 */ + mtspr 27, %r31 + mtspr 54, %r31 /* DECAR */ + mtspr 58, %r31 /* CSRR0-1 */ + mtspr 59, %r31 + mtspr 61, %r31 /* DEAR */ + mtspr 256, %r31 /* USPRG0 */ + mtspr 272, %r31 /* SPRG1-7 */ + mtspr 273, %r31 + mtspr 274, %r31 + mtspr 275, %r31 + mtspr 276, %r31 + mtspr 277, %r31 + mtspr 278, %r31 + mtspr 279, %r31 + mtspr 285, %r31 /* TBU */ + mtspr 284, %r31 /* TBL */ +#if 0 + mtspr 318, %r31 /* DVC1-2 */ + mtspr 319, %r31 +#endif + mtspr 562, %r31 /* DBCNT */ + mtspr 570, %r31 /* MCSRR0 */ + mtspr 571, %r31 /* MCSRR1 */ + mtspr 604, %r31 /* SPRG8-9 */ + mtspr 605, %r31 + +#if BOOT_PERFORM_CORE_INIT + /* + * *Finally* the TLB0 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/startup/e200/devices/SPC56ELxx/boot.s b/os/common/startup/e200/devices/SPC56ELxx/boot.s deleted file mode 100644 index 9446823e5..000000000 --- a/os/common/startup/e200/devices/SPC56ELxx/boot.s +++ /dev/null @@ -1,405 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC56ELxx/boot.s - * @brief SPC56ELxx boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#if !defined(__DOXYGEN__) - - /* BAM record.*/ - .section .boot, "ax" - -#if BOOT_USE_VLE - .long 0x015A0000 -#else - .long 0x005A0000 -#endif - .long _reset_address - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: - bl _coreinit - bl _ivinit - -#if BOOT_RELOCATE_IN_RAM - /* - * Image relocation in RAM. - */ - lis %r4, __ram_reloc_start__@h - ori %r4, %r4, __ram_reloc_start__@l - lis %r5, __ram_reloc_dest__@h - ori %r5, %r5, __ram_reloc_dest__@l - lis %r6, __ram_reloc_end__@h - ori %r6, %r6, __ram_reloc_end__@l -.relloop: - cmpl cr0, %r4, %r6 - bge cr0, .relend - lwz %r7, 0(%r4) - addi %r4, %r4, 4 - stw %r7, 0(%r5) - addi %r5, %r5, 4 - b .relloop -.relend: - lis %r3, _boot_address@h - ori %r3, %r3, _boot_address@l - mtctr %r3 - bctrl -#else - b _boot_address -#endif - -#if BOOT_PERFORM_CORE_INIT - .align 2 -_ramcode: - tlbwe - isync - blr -#endif /* BOOT_PERFORM_CORE_INIT */ - - .align 2 -_coreinit: -#if BOOT_PERFORM_CORE_INIT - /* - * Invalidating all TLBs except TLB0. - */ - lis %r3, 0 - mtspr 625, %r3 /* MAS1 */ - mtspr 626, %r3 /* MAS2 */ - mtspr 627, %r3 /* MAS3 */ - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h - mtspr 624, %r3 /* MAS0 */ - tlbwe - - /* - * TLB1 allocated to internal RAM. - */ - lis %r3, TLB1_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB1_MAS1@h - ori %r3, %r3, TLB1_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB1_MAS2@h - ori %r3, %r3, TLB1_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB1_MAS3@h - ori %r3, %r3, TLB1_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB2 allocated to internal Peripherals Bridge A. - */ - lis %r3, TLB2_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB2_MAS1@h - ori %r3, %r3, TLB2_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB2_MAS2@h - ori %r3, %r3, TLB2_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB2_MAS3@h - ori %r3, %r3, TLB2_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB3 allocated to internal Peripherals Bridge B. - */ - lis %r3, TLB3_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB3_MAS1@h - ori %r3, %r3, TLB3_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB3_MAS2@h - ori %r3, %r3, TLB3_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB3_MAS3@h - ori %r3, %r3, TLB3_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB4 allocated to on-platform peripherals. - */ - lis %r3, TLB4_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB4_MAS1@h - ori %r3, %r3, TLB4_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB4_MAS2@h - ori %r3, %r3, TLB4_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB4_MAS3@h - ori %r3, %r3, TLB4_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * TLB5 allocated to on-platform peripherals. - */ - lis %r3, TLB5_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB5_MAS1@h - ori %r3, %r3, TLB5_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB5_MAS2@h - ori %r3, %r3, TLB5_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB5_MAS3@h - ori %r3, %r3, TLB5_MAS3@l - mtspr 627, %r3 /* MAS3 */ - tlbwe - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Special function registers clearing, required in order to avoid - * possible problems with lockstep mode. - */ - mtcrf 0xFF, %r31 - mtspr 9, %r31 /* CTR */ - mtspr 22, %r31 /* DEC */ - mtspr 26, %r31 /* SRR0-1 */ - mtspr 27, %r31 - mtspr 54, %r31 /* DECAR */ - mtspr 58, %r31 /* CSRR0-1 */ - mtspr 59, %r31 - mtspr 61, %r31 /* DEAR */ - mtspr 256, %r31 /* USPRG0 */ - mtspr 272, %r31 /* SPRG1-7 */ - mtspr 273, %r31 - mtspr 274, %r31 - mtspr 275, %r31 - mtspr 276, %r31 - mtspr 277, %r31 - mtspr 278, %r31 - mtspr 279, %r31 - mtspr 285, %r31 /* TBU */ - mtspr 284, %r31 /* TBL */ -#if 0 - mtspr 318, %r31 /* DVC1-2 */ - mtspr 319, %r31 -#endif - mtspr 562, %r31 /* DBCNT */ - mtspr 570, %r31 /* MCSRR0 */ - mtspr 571, %r31 /* MCSRR1 */ - mtspr 604, %r31 /* SPRG8-9 */ - mtspr 605, %r31 - -#if BOOT_PERFORM_CORE_INIT - /* - * *Finally* the TLB0 is re-allocated to flash, note, the final phase - * is executed from RAM. - */ - lis %r3, TLB0_MAS0@h - mtspr 624, %r3 /* MAS0 */ - lis %r3, TLB0_MAS1@h - ori %r3, %r3, TLB0_MAS1@l - mtspr 625, %r3 /* MAS1 */ - lis %r3, TLB0_MAS2@h - ori %r3, %r3, TLB0_MAS2@l - mtspr 626, %r3 /* MAS2 */ - lis %r3, TLB0_MAS3@h - ori %r3, %r3, TLB0_MAS3@l - mtspr 627, %r3 /* MAS3 */ - mflr %r4 - lis %r6, _ramcode@h - ori %r6, %r6, _ramcode@l - lis %r7, 0x40010000@h - mtctr %r7 - lwz %r3, 0(%r6) - stw %r3, 0(%r7) - lwz %r3, 4(%r6) - stw %r3, 4(%r7) - lwz %r3, 8(%r6) - stw %r3, 8(%r7) - bctrl - mtlr %r4 -#endif /* BOOT_PERFORM_CORE_INIT */ - - /* - * Branch prediction enabled. - */ - li %r3, BOOT_BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - /* - * Cache invalidated and then enabled. - */ - li %r3, LICSR1_ICINV - mtspr 1011, %r3 /* LICSR1 */ -.inv: mfspr %r3, 1011 /* LICSR1 */ - andi. %r3, %r3, LICSR1_ICINV - bne .inv - lis %r3, BOOT_LICSR1_DEFAULT@h - ori %r3, %r3, BOOT_LICSR1_DEFAULT@l - mtspr 1011, %r3 /* LICSR1 */ - - blr - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, BOOT_MSR_DEFAULT@h - ori %r3, %r3, BOOT_MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - /* IVORs initialization.*/ - lis %r3, _unhandled_exception@h - ori %r3, %r3, _unhandled_exception@l - - mtspr 400, %r3 /* IVOR0-15 */ - mtspr 401, %r3 - mtspr 402, %r3 - mtspr 403, %r3 - mtspr 404, %r3 - mtspr 405, %r3 - mtspr 406, %r3 - mtspr 407, %r3 - mtspr 408, %r3 - mtspr 409, %r3 - mtspr 410, %r3 - mtspr 411, %r3 - mtspr 412, %r3 - mtspr 413, %r3 - mtspr 414, %r3 - mtspr 415, %r3 - mtspr 528, %r3 /* IVOR32-34 */ - mtspr 529, %r3 - mtspr 530, %r3 - - blr - - .section .handlers, "ax" - - /* - * Unhandled exceptions handler. - */ - .weak _unhandled_exception - .type _unhandled_exception, @function -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h deleted file mode 100644 index 0c3af3957..000000000 --- a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file boot.h - * @brief Boot parameters for the SPC57EMxx_HSM. - * @{ - */ - -#ifndef BOOT_H -#define BOOT_H - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name BUCSR registers definitions - * @{ - */ -#define BUCSR_BPEN 0x00000001 -#define BUCSR_BALLOC_BFI 0x00000200 -/** @} */ - -/** - * @name MSR register definitions - * @{ - */ -#define MSR_WE 0x00040000 -#define MSR_CE 0x00020000 -#define MSR_EE 0x00008000 -#define MSR_PR 0x00004000 -#define MSR_ME 0x00001000 -#define MSR_DE 0x00000200 -#define MSR_IS 0x00000020 -#define MSR_DS 0x00000010 -#define MSR_RI 0x00000002 -/** @} */ - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/* - * BUCSR default settings. - */ -#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) -#endif - -/* - * MSR default settings. - */ -#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) -#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* BOOT_H */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s b/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s deleted file mode 100644 index f9eb2d52d..000000000 --- a/os/common/startup/e200/devices/SPC57EMxx_HSM/boot.s +++ /dev/null @@ -1,208 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/boot.s - * @brief SPC57EMxx_HSM boot-related code. - * - * @addtogroup PPC_BOOT - * @{ - */ - -#include "boot.h" - -#define HSBI_CCR 0xA3F14004 -#define HSBI_CCR_CE 0x00000001 -#define HSBI_CCR_INV 0x00000002 - -#if !defined(__DOXYGEN__) - - /* Boot record.*/ - .section .boot, "ax" - - .long 0xFFFF0000 - .long 0xFFFF0000 - .long 0xFFFFFFFF - .long _reset_address - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - .long 0xFFFFFFFF - - .align 2 - .globl _reset_address - .type _reset_address, @function -_reset_address: - bl _coreinit - bl _ivinit - b _boot_address - - .align 2 -_coreinit: -#if 0 - /* - * Cache invalidate and enable. - */ - lis %r7, HSBI_CCR@h - ori %r7, %r7, HSBI_CCR@l - li %r0, HSBI_CCR_INV | HSBI_CCR_CE - stw %r0, 0(%r7) -.inv: - lwz %r0, 0(%r7) - andi. %r0, %r0, HSBI_CCR_INV - bne+ %cr0, .inv -#endif - - /* - * RAM clearing, this device requires a write to all RAM location in - * order to initialize the ECC detection hardware, this is going to - * slow down the startup but there is no way around. - */ - xor %r0, %r0, %r0 - xor %r1, %r1, %r1 - xor %r2, %r2, %r2 - xor %r3, %r3, %r3 - xor %r4, %r4, %r4 - xor %r5, %r5, %r5 - xor %r6, %r6, %r6 - xor %r7, %r7, %r7 - xor %r8, %r8, %r8 - xor %r9, %r9, %r9 - xor %r10, %r10, %r10 - xor %r11, %r11, %r11 - xor %r12, %r12, %r12 - xor %r13, %r13, %r13 - xor %r14, %r14, %r14 - xor %r15, %r15, %r15 - xor %r16, %r16, %r16 - xor %r17, %r17, %r17 - xor %r18, %r18, %r18 - xor %r19, %r19, %r19 - xor %r20, %r20, %r20 - xor %r21, %r21, %r21 - xor %r22, %r22, %r22 - xor %r23, %r23, %r23 - xor %r24, %r24, %r24 - xor %r25, %r25, %r25 - xor %r26, %r26, %r26 - xor %r27, %r27, %r27 - xor %r28, %r28, %r28 - xor %r29, %r29, %r29 - xor %r30, %r30, %r30 - xor %r31, %r31, %r31 - lis %r4, __ram_start__@h - ori %r4, %r4, __ram_start__@l - lis %r5, __ram_end__@h - ori %r5, %r5, __ram_end__@l -.cleareccloop: - cmpl %cr0, %r4, %r5 - bge %cr0, .cleareccend - stmw %r16, 0(%r4) - addi %r4, %r4, 64 - b .cleareccloop -.cleareccend: - - /* - * Branch prediction enabled. - */ - li %r3, BUCSR_DEFAULT - mtspr 1013, %r3 /* BUCSR */ - - blr - - /* - * Exception vectors initialization. - */ - .align 2 -_ivinit: - /* MSR initialization.*/ - lis %r3, MSR_DEFAULT@h - ori %r3, %r3, MSR_DEFAULT@l - mtMSR %r3 - - /* IVPR initialization.*/ - lis %r3, __ivpr_base__@h - ori %r3, %r3, __ivpr_base__@l - mtIVPR %r3 - - blr - - .section .ivors, "ax" - - .globl IVORS -IVORS: -IVOR0: b _IVOR0 - .align 4 -IVOR1: b _IVOR1 - .align 4 -IVOR2: b _IVOR2 - .align 4 -IVOR3: b _IVOR3 - .align 4 -IVOR4: b _IVOR4 - .align 4 -IVOR5: b _IVOR5 - .align 4 -IVOR6: b _IVOR6 - .align 4 -IVOR7: b _IVOR7 - .align 4 -IVOR8: b _IVOR8 - .align 4 -IVOR9: b _IVOR9 - .align 4 -IVOR10: b _IVOR10 - .align 4 -IVOR11: b _IVOR11 - .align 4 -IVOR12: b _IVOR12 - .align 4 -IVOR13: b _IVOR13 - .align 4 -IVOR14: b _IVOR14 - .align 4 -IVOR15: b _IVOR15 - - .section .handlers, "ax" - - /* - * Default IVOR handlers. - */ - .align 2 - .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 - .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 - .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 -_IVOR0: -_IVOR1: -_IVOR2: -_IVOR3: -_IVOR5: -_IVOR6: -_IVOR7: -_IVOR8: -_IVOR9: -_IVOR11: -_IVOR12: -_IVOR13: -_IVOR14: -_IVOR15: - .global _unhandled_exception -_unhandled_exception: - b _unhandled_exception - -#endif /* !defined(__DOXYGEN__) */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h deleted file mode 100644 index e57e02688..000000000 --- a/os/common/startup/e200/devices/SPC57EMxx_HSM/intc.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/intc.h - * @brief SPC57EMxx_HSM INTC module header. - * - * @addtogroup INTC - * @{ - */ - -#ifndef INTC_H -#define INTC_H - -/*===========================================================================*/ -/* Module constants. */ -/*===========================================================================*/ - -/** - * @name INTC addresses - * @{ - */ -#define INTC_BASE 0xA3F48000 -#define INTC_IACKR_ADDR (INTC_BASE + 0x20) -#define INTC_EOIR_ADDR (INTC_BASE + 0x30) -/** @} */ - -/** - * @brief INTC priority levels. - */ -#define INTC_PRIORITY_LEVELS 16U - -/*===========================================================================*/ -/* Module pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module macros. */ -/*===========================================================================*/ - -/** - * @name INTC-related macros - * @{ - */ -#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) -#define INTC_MPROT (*((volatile uint32_t *)(INTC_BASE + 4))) -#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) -#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x20 + ((n) * sizeof (uint32_t))))) -#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x30 + ((n) * sizeof (uint32_t))))) -#define INTC_PSR(n) (*((volatile uint16_t *)(INTC_BASE + 0x60 + ((n) * sizeof (uint16_t))))) -/** @} */ - -/** - * @brief Core selection macros for PSR register. - */ -#define INTC_PSR_CORE4 0x8000 - -/** - * @brief PSR register content helper - */ -#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Module inline functions. */ -/*===========================================================================*/ - -#endif /* INTC_H */ - -/** @} */ diff --git a/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h b/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h deleted file mode 100644 index a6f86c15d..000000000 --- a/os/common/startup/e200/devices/SPC57EMxx_HSM/ppcparams.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file SPC57EMxx_HSM/ppcparams.h - * @brief PowerPC parameters for the SPC57EMxx_HSM. - * - * @defgroup PPC_SPC57EMxx_HSM SPC57EMxx_HSM Specific Parameters - * @ingroup PPC_SPECIFIC - * @details This file contains the PowerPC specific parameters for the - * SPC57EMxx_HSM platform. - * @{ - */ - -#ifndef PPCPARAMS_H -#define PPCPARAMS_H - -/** - * @brief Family identification macro. - */ -#define PPC_SPC560Dxx - -/** - * @brief Alternate identification macro. - */ -#define PPC_SPC57EMxx_HSM - -/** - * @brief PPC core model. - */ -#define PPC_VARIANT PPC_VARIANT_e200z0 - -/** - * @brief Number of cores. - */ -#define PPC_CORE_NUMBER 1 - -/** - * @brief Number of writable bits in IVPR register. - */ -#define PPC_IVPR_BITS 20 - -/** - * @brief IVORx registers support. - */ -#define PPC_SUPPORTS_IVORS FALSE - -/** - * @brief Book E instruction set support. - */ -#define PPC_SUPPORTS_BOOKE FALSE - -/** - * @brief VLE instruction set support. - */ -#define PPC_SUPPORTS_VLE TRUE - -/** - * @brief Supports VLS Load/Store Multiple Volatile instructions. - */ -#define PPC_SUPPORTS_VLE_MULTI TRUE - -/** - * @brief Supports the decrementer timer. - */ -#define PPC_SUPPORTS_DECREMENTER FALSE - -/** - * @brief Number of interrupt sources. - */ -#define PPC_NUM_VECTORS 64 - -#endif /* PPCPARAMS_H */ - -/** @} */ -- cgit v1.2.3