From 822ca41c6b7812bfc525d359ca62f0a788638151 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 5 Mar 2012 20:39:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4026 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/OTGv1/stm32_otg.h | 990 +++++++++++++++++-------------- 1 file changed, 537 insertions(+), 453 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/os/hal/platforms/STM32/OTGv1/stm32_otg.h index 015cb0243..45b1497d1 100644 --- a/os/hal/platforms/STM32/OTGv1/stm32_otg.h +++ b/os/hal/platforms/STM32/OTGv1/stm32_otg.h @@ -6,7 +6,7 @@ ChibiOS/RT is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or + the Free software Foundation; either version 3 of the License, or (at your option) any later version. ChibiOS/RT is distributed in the hope that it will be useful, @@ -30,7 +30,7 @@ #define _STM32_OTG_H_ /** - * @brief number of the implemented endpoints. + * @brief Number of the implemented endpoints. * @details This value does not include the endpoint 0 that is always present. */ #define STM32_OTG_ENDOPOINTS_NUMBER 3 @@ -53,7 +53,7 @@ typedef struct { } stm32_otg_host_chn_t; /** - * @brief Device Input endpoint registers group. + * @brief Device input endpoint registers group. */ typedef struct { volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint control @@ -71,7 +71,7 @@ typedef struct { } stm32_otg_in_ep_t; /** - * @brief Device Output endpoint registers group. + * @brief Device output endpoint registers group. */ typedef struct { volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint control @@ -103,9 +103,9 @@ typedef struct { volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop register. */ volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ - volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size + volatile uint32_t DIEPTXF0; /**< @brief endpoint 0 transmit FIFO size register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue + volatile uint32_t HNPTXSTS; /**< @brief non-periodic transmit FIFO/queue status register. */ volatile uint32_t resvd30; volatile uint32_t resvd34; @@ -138,14 +138,14 @@ typedef struct { volatile uint32_t DCTL; /**< @brief Device control register. */ volatile uint32_t DSTS; /**< @brief Device status register. */ volatile uint32_t resvd80C; - volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common interrupt - mask register. */ - volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common interrupt - mask register. */ + volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common + interrupt mask register. */ + volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common + interrupt mask register. */ volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt register. */ - volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt mask - register. */ + volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt + mask register. */ volatile uint32_t resvd820; volatile uint32_t resvd824; volatile uint32_t DVBUSDIS; /**< @brief Device VBUS Discharge time @@ -168,238 +168,263 @@ typedef struct { volatile uint32_t resvdE04[127]; } stm32_otg_t; -/* - * GOTGCTL register bit definitions. - */ -#define GOTGCTL_BSesVld (1<<19) /**< B-Session Valid. */ -#define GOTGCTL_ASesVld (1<<18) /**< A-Session Valid. */ -#define GOTGCTL_Dbnctime (1<<17) /**< Long/Short Debounce time. */ -#define GOTGCTL_ConIDSts (1<<16) /**< Connector ID status. */ -#define GOTGCTL_DevHNPEn (1<<11) /**< Device HNP Enabled. */ -#define GOTGCTL_HstSetHNPEn (1<<10) /**< Host Set HNP Enable. */ -#define GOTGCTL_HNPReq (1<<9) /**< HNP Request. */ -#define GOTGCTL_HstNegScs (1<<8) /**< Host Negotiation Success. */ -#define GOTGCTL_SesReq (1<<1) /**< Session Request. */ -#define GOTGCTL_SesReqScs (1<<0) /**< Session Request Success. */ +/** + * @name GOTGCTL register bit definitions + * @{ + */ +#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */ +#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */ +#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */ +#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */ +#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */ +#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */ +#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */ +#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */ +#define GOTGCTL_SRQ (1U<<1) /**< Session request. */ +#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */ +/** @} */ -/* - * GOTGINT register bit definitions. +/** + * @name GOTGINT register bit definitions + * @{ */ -#define GOTGINT_DbnceDone (1<<19) /**< Debounce Done. */ -#define GOTGINT_ADevTOUTChg (1<<18) /**< A-Device timeout Change. */ -#define GOTGINT_HstNegDet (1<<17) /**< Host Negotiation Detected. */ -#define GOTGINT_HstNegSucStsChng (1<<9) /**< Host Negotiation Success status - Change. */ -#define GOTGINT_SesReqSucStsChng (1<<8) /**< Session Request Success status - Change. */ -#define GOTGINT_SesEndDet (1<<2) /**< Session End Detected. */ +#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */ +#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */ +#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */ +#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success + status change. */ +#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success + status change. */ +#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */ +/** @} */ -/* - * GAHBCFG register bit definitions. +/** + * @name GAHBCFG register bit definitions + * @{ */ -#define GAHBCFG_PTxFEmpLvl (1<<8) /**< periodic TxFIFO Empty Level. */ -#define GAHBCFG_NPTxFEmpLvl (1<<7) /**< Non-periodic TxFIFO Empty - Level. */ -#define GAHBCFG_GlblIntrMsk (1<<0) /**< Global interrupt mask. */ +#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty + level. */ +#define GAHBCFG_TXFELVL (1U<<7) /**< non-periodic TxFIFO empty + level. */ +#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */ +/** @} */ -/* - * GUSBCFG register bit definitions. - */ -#define GUSBCFG_ForceDevMode (1<<30) /**< Force Device Mode. */ -#define GUSBCFG_ForceHstMode (1<<29) /**< Force Host Mode. */ -#define GUSBCFG_TxEndDelay (1<<28) /**< Tx End Delay. */ -#define GUSBCFG_USBTrdTim_MASK (15<<10)/**< USB Turnaround time field mask.*/ -#define GUSBCFG_USBTrdTim(n) ((n)<<10)/**< USB Turnaround time field - value. */ -#define GUSBCFG_HNPCap (1<<9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCap (1<<8) /**< SRP-Capable. */ -#define GUSBCFG_PHYSel (1<<6) /**< USB 2.0 High-Speed PHY or USB - 1.1 Full-Speed Serial - Transceiver Select. */ -#define GUSBCFG_TOutCal_MASK (7<<0) /**< HS/FS timeout Calibration field - mask. */ -#define GUSBCFG_TOutCal_(n) ((n)<<0)/**< HS/FS timeout Calibration field - value. */ +/** + * @name GUSBCFG register bit definitions + * @{ + */ +#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */ +#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */ +#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */ +#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field + mask. */ +#define GUSBCFG_TRDT(n) ((n##U)<<10)/**< USB Turnaround time field + value. */ +#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */ +#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */ +#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or + USB 1.1 Full-Speed serial + transceiver Select. */ +#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration + field mask. */ +#define GUSBCFG_TOCAL(n) ((n##U)<<0) /**< HS/FS timeout calibration + field value. */ +/** @} */ -/* - * GRSTCTL register bit definitions. - */ -#define GRSTCTL_AHBIdle (1u<<31)/**< AHB Master Idle. */ -#define GRSTCTL_DMAReq (1<<30) /**< DMA Request Signal. */ -#define GRSTCTL_TxFNum_MASK (31<<6) /**< TxFIFO number field mask. */ -#define GRSTCTL_TxFNum(n) ((n)<<6)/**< TxFIFO number field value. */ -#define GRSTCTL_TxFFlsh (1<<5) /**< TxFIFO Flush. */ -#define GRSTCTL_RxFFlsh (1<<4) /**< RxFIFO Flush. */ -#define GRSTCTL_INTknQFlsh (1<<3) /**< IN Token Sequence Learning - queue Flush. */ -#define GRSTCTL_FrmCntrRst (1<<2) /**< Host frame Counter Reset. */ -#define GRSTCTL_HSftRst (1<<1) /**< HClk Soft Reset. */ -#define GRSTCTL_CSftRst (1<<0) /**< Core Soft Reset. */ +/** + * @name GRSTCTL register bit definitions + * @{ + */ +#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */ +#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */ +#define GRSTCTL_TXFNUM(n) ((n##U)<<6) /**< TxFIFO number field value. */ +#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */ +#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */ +#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */ +#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */ +#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */ +/** @} */ -/* - * GINTSTS register bit definitions. - */ -#define GINTSTS_WkUpInt (1u<<31)/**< Resume/Remote Wakeup Detected - interrupt. */ -#define GINTSTS_SessReqInt (1<<30) /**< Session Request/New Session - Detected interrupt. */ -#define GINTSTS_DisconnInt (1<<29) /**< Disconnect Detected interrupt. */ -#define GINTSTS_ConIDStsChng (1<<28) /**< Connector ID status Change. */ -#define GINTSTS_LPM_Int (1<<27) /**< LPM Transaction Received - interrupt. */ -#define GINTSTS_PTxFEmp (1<<26) /**< periodic TxFIFO Empty. */ -#define GINTSTS_HChInt (1<<25) /**< Host channels interrupt. */ -#define GINTSTS_PrtInt (1<<24) /**< Host port interrupt. */ -#define GINTSTS_ResetDet (1<<23) /**< Reset Detected interrupt. */ -#define GINTSTS_FetSusp (1<<22) /**< Data Fetch Suspended. */ -#define GINTSTS_incomplP (1<<21) /**< Incomplete periodic transfer. */ -#define GINTSTS_incompISOOUT (1<<21) /**< Incomplete Isochronous OUT - transfer. */ -#define GINTSTS_incompISOIN (1<<20) /**< Incomplete Isochronous IN - transfer. */ -#define GINTSTS_OEPInt (1<<19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPInt (1<<18) /**< IN endpoints interrupt. */ -#define GINTSTS_EPMis (1<<17) /**< endpoint Mismatch interrupt. */ -#define GINTSTS_EOPF (1<<15) /**< End of periodic frame - interrupt. */ -#define GINTSTS_ISOOutDrop (1<<14) /**< Isochronous OUT Packet Dropped - interrupt. */ -#define GINTSTS_EnumDone (1<<13) /**< Enumeration Done. */ -#define GINTSTS_USBRst (1<<12) /**< USB Reset. */ -#define GINTSTS_USBSusp (1<<11) /**< USB Suspend. */ -#define GINTSTS_ErlySusp (1<<10) /**< Early Suspend. */ -#define GINTSTS_GOUTNakEff (1<<7) /**< Global OUT NAK Effective. */ -#define GINTSTS_GINNakEff (1<<6) /**< Global IN Non-periodic NAK - Effective. */ -#define GINTSTS_NPTxFEmp (1<<5) /**< Non-periodic TxFIFO Empty. */ -#define GINTSTS_RxFLvl (1<<4) /**< RxFIFO Non-Empty. */ -#define GINTSTS_Sof (1<<3) /**< Start of (micro)frame. */ -#define GINTSTS_OTGInt (1<<2) /**< OTG interrupt. */ -#define GINTSTS_ModeMis (1<<1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CurMod (1<<0) /**< Current Mode of Operation. */ +/** + * @name GINTSTS register bit definitions + * @{ + */ +#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup + detected interrupt. */ +#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session + detected interrupt. */ +#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected + interrupt. */ +#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/ +#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */ +#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */ +#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */ +#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic + transfer. */ +#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT + transfer. */ +#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN + transfer. */ +#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */ +#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */ +#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame + interrupt. */ +#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet + dropped interrupt. */ +#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */ +#define GINTSTS_USBRST (1U<<12) /**< USB reset. */ +#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */ +#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */ +#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */ +#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK + effective. */ +#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */ +#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */ +#define GINTSTS_SOF (1U<<3) /**< Start of frame. */ +#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */ +#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */ +#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */ +/** @} */ -/* - * GINTMSK register bit definitions. - */ -#define GINTMSK_WkUpIntMsk (1u<<31)/**< Resume/Remote Wakeup Detected - interrupt mask. */ -#define GINTMSK_SessReqIntMsk (1<<30) /**< Session Request/New Session - Detected interrupt mask. */ -#define GINTMSK_DisconnIntMsk (1<<29) /**< Disconnect Detected interrupt - mask. */ -#define GINTMSK_ConIDStsChngMsk (1<<28) /**< Connector ID status Change - mask. */ -#define GINTMSK_LPM_IntMsk (1<<27) /**< LPM Transaction Received - interrupt mask. */ -#define GINTMSK_PTxFEmpMsk (1<<26) /**< periodic TxFIFO Empty mask. */ -#define GINTMSK_HChIntMsk (1<<25) /**< Host channels interrupt mask. */ -#define GINTMSK_PrtIntMsk (1<<24) /**< Host port interrupt mask. */ -#define GINTMSK_ResetDetMsk (1<<23) /**< Reset Detected interrupt mask. */ -#define GINTMSK_FetSuspMsk (1<<22) /**< Data Fetch Suspended mask. */ -#define GINTMSK_incomplPMsk (1<<21) /**< Incomplete periodic transfer - mask. */ -#define GINTMSK_incompISOOUTMsk (1<<21) /**< Incomplete Isochronous OUT - transfer mask. */ -#define GINTMSK_incompISOINMsk (1<<20) /**< Incomplete Isochronous IN - transfer mask. */ -#define GINTMSK_OEPIntMsk (1<<19) /**< OUT endpoints interrupt mask. */ -#define GINTMSK_IEPIntMsk (1<<18) /**< IN endpoints interrupt mask. */ -#define GINTMSK_EPMisMsk (1<<17) /**< endpoint Mismatch interrupt - mask. */ -#define GINTMSK_EOPFMsk (1<<15) /**< End of periodic frame interrupt - mask. */ -#define GINTMSK_ISOOutDropMsk (1<<14) /**< Isochronous OUT Packet Dropped - interrupt mask. */ -#define GINTMSK_EnumDoneMsk (1<<13) /**< Enumeration Done mask. */ -#define GINTMSK_USBRstMsk (1<<12) /**< USB Reset mask. */ -#define GINTMSK_USBSuspMsk (1<<11) /**< USB Suspend mask. */ -#define GINTMSK_ErlySuspMsk (1<<10) /**< Early Suspend mask. */ -#define GINTMSK_GOUTNakEffMsk (1<<7) /**< Global OUT NAK Effective mask. */ -#define GINTMSK_GINNakEffMsk (1<<6) /**< Global Non-periodic IN NAK - Effective mask. */ -#define GINTMSK_NPTxFEmpMsk (1<<5) /**< Non-periodic TxFIFO Empty mask.*/ -#define GINTMSK_RxFLvlMsk (1<<4) /**< Receive FIFO Non-Empty mask. */ -#define GINTMSK_SofMsk (1<<3) /**< Start of (micro)frame mask. */ -#define GINTMSK_OTGIntMsk (1<<2) /**< OTG interrupt mask. */ -#define GINTMSK_ModeMisMsk (1<<1) /**< Mode Mismatch interrupt mask. */ +/** + * @name GINTMSK register bit definitions + * @{ + */ +#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup + detected interrupt mask. */ +#define GINTMSK_SRQM (1U<<30) /**< Session request/New session + detected interrupt mask. */ +#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected + interrupt mask. */ +#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change + mask. */ +#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/ +#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt + mask. */ +#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */ +#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic + transfer mask. */ +#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT + transfer mask. */ +#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN + transfer mask. */ +#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt + mask. */ +#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt + mask. */ +#define GINTMSK_EPMISM (1U<<17) /**< Endpoint Mismatch interrupt + mask. */ +#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame + interrupt mask. */ +#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet + dropped interrupt mask. */ +#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */ +#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */ +#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */ +#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */ +#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective + mask. */ +#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK + effective mask. */ +#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty + mask. */ +#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty + mask. */ +#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/ +#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */ +#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt + mask. */ +/** @} */ -/* - * GRXSTSR register bit definitions. - */ -#define GRXSTSR_PktSts_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSR_PktSts(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSR_DPID_MASK (3<<15) /**< Data PID mask. */ -#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSR_BCnt_MASK (0x7FF<<4) /**< Byte Count mask. */ -#define GRXSTSR_BCnt_OFF 4 /**< Byte Count offset. */ -#define GRXSTSR_BCnt(n) ((n)<<5) /**< Byte Count value. */ -#define GRXSTSR_ChNum_MASK (15<<0) /**< channel number mask. */ -#define GRXSTSR_ChNum(n) ((n)<<0) /**< channel number value. */ -#define GRXSTSR_EPNum_MASK (15<<0) /**< endpoint number mask. */ -#define GRXSTSR_EPNum(n) ((n)<<0) /**< endpoint number value. */ +/** + * @name GRXSTSR register bit definitions + * @{ + */ +#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */ +#define GRXSTSR_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */ +#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1) +#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2) +#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3) +#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4) +#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6) +#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRXSTSR_DPID(n) ((n##U)<<15)/**< Data PID value. */ +#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRXSTSR_BCNT(n) ((n##U)<<4) /**< Byte count value. */ +#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRXSTSR_CHNUM(n) ((n##U)<<0) /**< Channel number value. */ +#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRXSTSR_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */ +/** @} */ -/* - * GRXSTSP register bit definitions. - */ -#define GRXSTSP_PktSts_MASK (15<<17) /**< Packet status mask. */ -#define GRXSTSP_PktSts(n) ((n)<<17) /**< Packet status value. */ -#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PktSts(1) -#define GRXSTSP_OUT_DATA GRXSTSP_PktSts(2) -#define GRXSTSP_OUT_COMP GRXSTSP_PktSts(3) -#define GRXSTSP_SETUP_COMP GRXSTSP_PktSts(4) -#define GRXSTSP_SETUP_DATA GRXSTSP_PktSts(6) -#define GRXSTSP_DPID_MASK (3<<15) /**< Data PID mask. */ -#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */ -#define GRXSTSP_BCnt_MASK (0x7FF<<4) /**< Byte Count mask. */ -#define GRXSTSP_BCnt_OFF 4 /**< Byte Count offset. */ -#define GRXSTSP_BCnt(n) ((n)<<5) /**< Byte Count value. */ -#define GRXSTSP_ChNum_MASK (15<<0) /**< channel number mask. */ -#define GRXSTSP_ChNum_OFF 0 /**< channel number mask. */ -#define GRXSTSP_ChNum(n) ((n)<<0) /**< channel number value. */ -#define GRXSTSP_EPNum_MASK (15<<0) /**< endpoint number mask. */ -#define GRXSTSP_EPNum_OFF 0 /**< endpoint number offset.*/ -#define GRXSTSP_EPNum(n) ((n)<<0) /**< endpoint number value. */ +/** + * @name GRXSTSP register bit definitions + * @{ + */ +#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */ +#define GRXSTSP_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */ +#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1) +#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2) +#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3) +#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4) +#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6) +#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */ +#define GRXSTSP_DPID(n) ((n##U)<<15)/**< Data PID value. */ +#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */ +#define GRXSTSP_BCNT(n) ((n##U)<<4) /**< Byte count value. */ +#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */ +#define GRXSTSP_CHNUM(n) ((n##U)<<0) /**< Channel number value. */ +#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */ +#define GRXSTSP_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */ +/** @} */ -/* - * GRXFSIZ register bit definitions. +/** + * @name GRXFSIZ register bit definitions + * @{ */ -#define GRXFSIZ_RxFDep_MASK (0xFFFF<<0) /**< RxFIFO Depth mask. */ -#define GRXFSIZ_RxFDep(n) ((n)<<0) /**< RxFIFO Depth value. */ +#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */ +#define GRXFSIZ_RXFD(n) ((n##U)<<0) /**< RxFIFO depth value. */ +/** @} */ -/* - * GNPTXFSIZ register bit definitions. +/** + * @name GNPTXFSIZ register bit definitions + * @{ */ -#define GNPTXFSIZ_NPTxFDep_MASK (0xFFFFu<<16)/**< Non-periodic TxFIFO Depth - mask. */ -#define GNPTXFSIZ_NPTxFDep(n) ((n)<<16) /**< Non-periodic TxFIFO Depth - value. */ -#define GNPTXFSIZ_NPTxFStAddr_MASK (0xFFFF<<0) /**< Non-periodic transmit RAM - Start Address mask. */ -#define GNPTXFSIZ_NPTxFStAddr(n) ((n)<<0) /**< Non-periodic transmit RAM - Start Address value. */ +#define GNPTXFSIZ_NPTXFD_MASK (0xFFFFU<<16)/**< Non-periodic TxFIFO depth + mask. */ +#define GNPTXFSIZ_NPTXFD(n) ((n##U)<<16)/**< Non-periodic TxFIFO depth + value. */ +#define GNPTXFSIZ_NPTXFSA_MASK (0xFFFFU<<0)/**< Non-periodic transmit RAM + start address mask. */ +#define GNPTXFSIZ_NPTXFSA(n) ((n##U)<<0) /**< Non-periodic transmit RAM + start address value. */ +/** @} */ -/* - * GNPTXSTS register bit definitions. +/** + * @name GNPTXSTS register bit definitions + * @{ */ -#define GNPTXSTS_NPTxQTop_MASK (0x7F<<24) /**< Top of the Non-periodic - transmit Request queue +#define GNPTXSTS_NPTxQTop_MASK (0x7F<<24) /**< Top of the non-periodic + transmit request queue mask. */ -#define GNPTXSTS_NPTxQTop(n) ((n)<<24) /**< Top of the Non-periodic - transmit Request queue +#define GNPTXSTS_NPTxQTop(n) ((n)<<24) /**< Top of the non-periodic + transmit request queue value. */ -#define GNPTXSTS_NPTxQSpcAvail_MASK (0xFF<<16) /**< Non-periodic transmit - Request queue Space +#define GNPTXSTS_NPTxQSpcAvail_MASK (0xFF<<16) /**< non-periodic transmit + request queue Space Available mask. */ -#define GNPTXSTS_NPTxQSpcAvail(n) ((n)<<16) /**< Non-periodic transmit - Request queue Space +#define GNPTXSTS_NPTxQSpcAvail(n) ((n)<<16) /**< non-periodic transmit + request queue Space Available value. */ -#define GNPTXSTS_NPTxFSpcAvail_MASK (0xFFFF<<0) /**< Non-periodic TxFIFO +#define GNPTXSTS_NPTxFSpcAvail_MASK (0xFFFF<<0) /**< non-periodic TxFIFO Space Available mask. */ -#define GNPTXSTS_NPTxFSpcAvail(n) ((n)<<0) /**< Non-periodic TxFIFO +#define GNPTXSTS_NPTxFSpcAvail(n) ((n)<<0) /**< non-periodic TxFIFO Space Available value. */ +/** @} */ -/* - * HPTXFSIZ register bit definitions. +/** + * @name HPTXFSIZ register bit definitions + * @{ */ #define HPTXFSIZ_PTxFsize_MASK (0xFFFF<<16)/**< Host periodic TxFIFO Depth mask. */ @@ -409,9 +434,11 @@ typedef struct { Start Address mask. */ #define HPTXFSIZ_PTxFStAddr(n) ((n)<<0) /**< Host periodic TxFIFO Start Address value. */ +/** @} */ -/* - * DPTXFSIZ register bit definitions. +/** + * @name DPTXFSIZ register bit definitions + * @{ */ #define DPTXFSIZ_DPTxFsize_MASK (0xFFFF<<16 /**< Device periodic TxFIFO size mask. */ @@ -422,33 +449,39 @@ typedef struct { #define DPTXFSIZ_DPTxFStAddr(n) ((n)<<0) /**< Device periodic TxFIFO RAM Start Address value. */ +/** @} */ -/* - * HCFG register bit definitions. +/** + * @name HCFG register bit definitions + * @{ */ #define HCFG_ResValid_MASK (0xFF<<8) /**< Resume Validation Period mask. */ #define HCFG_ResValid(n) ((n)<<8) /**< Resume Validation Period value. */ -#define HCFG_Ena32KHzS (1<<7) /**< Enable 32-KHz Suspend +#define HCFG_Ena32KHzS (1U<<7) /**< enable 32-KHz suspend Mode. */ -#define HCFG_FSLSSupp (1<<2) /**< FS- and LS-Only +#define HCFG_FSLSSupp (1U<<2) /**< FS- and LS-Only Support. */ -#define HCFG_FSLSPclkSel_MASK (3<<0) /**< FS/LS PHY Clock Select +#define HCFG_FSLSPclkSel_MASK (3<<0) /**< FS/LS PHY clock Select mask. */ #define HCFG_FSLSPclkSel_30_60 (0<<0) /**< PHY clock is running at 30/60 MHz. */ -#define HCFG_FSLSPclkSel_48 (1<<0) /**< PHY clock is running at +#define HCFG_FSLSPclkSel_48 (1U<<0) /**< PHY clock is running at 48 MHz. */ +/** @} */ -/* - * HFIR register bit definitions. +/** + * @name HFIR register bit definitions + * @{ */ #define HFIR_FrInt_MASK (0xFFFF<<0) /**< frame interval mask. */ #define HFIR_FrInt(n) ((n)<<0) /**< frame interval value. */ +/** @} */ -/* - * HFNUM register bit definitions. +/** + * @name HFNUM register bit definitions + * @{ */ #define HFNUM_FrRem_MASK (0xFFFF<<16)/**< frame time Remaining mask. */ @@ -456,20 +489,22 @@ typedef struct { value. */ #define HFNUM_FrNum_MASK (0xFFFF<<0) /**< frame number mask. */ #define HFNUM_FrNum(n) ((n)<<0) /**< frame number value. */ +/** @} */ -/* - * HPTXSTS register bit definitions. +/** + * @name HPTXSTS register bit definitions + * @{ */ #define HPTXSTS_PTxQTop_MASK (0xFF<<24) /**< Top of the periodic - transmit Request queue + transmit request queue mask. */ #define HPTXSTS_PTxQTop(n) ((n)<<24) /**< Top of the periodic - transmit Request queue + transmit request queue value. */ -#define HPTXSTS_PTxQSpcAvail_MASK (0xFF<<16) /**< periodic transmit Request +#define HPTXSTS_PTxQSpcAvail_MASK (0xFF<<16) /**< periodic transmit request queue Space Available mask. */ -#define HPTXSTS_PTxQSpcAvail(n) ((n)<<16) /**< periodic transmit Request +#define HPTXSTS_PTxQSpcAvail(n) ((n)<<16) /**< periodic transmit request queue Space Available value. */ #define HPTXSTS_PTxFSpcAvail_MASK (0xFFFF<<0) /**< periodic transmit Data @@ -478,202 +513,224 @@ typedef struct { #define HPTXSTS_PTxFSpcAvail(n) ((n)<<0) /**< periodic transmit Data FIFO Space Available value. */ +/** @} */ -/* - * HAINT register bit definitions. +/** + * @name HAINT register bit definitions + * @{ */ #define HAINT_HAINT_MASK (0xFFFF<<0) /**< channel interrupts mask. */ #define HAINT_HAINT(n) ((n)<<0) /**< channel interrupts value. */ +/** @} */ -/* - * HAINTMSK register bit definitions. +/** + * @name HAINTMSK register bit definitions + * @{ */ #define HAINTMSK_HAINTMsk_MASK (0xFFFF<<0) /**< channel interrupt mask mask. */ #define HAINTMSK_HAINTMsk(n) ((n)<<0) /**< channel interrupt mask value. */ +/** @} */ -/* - * HPRT register bit definitions. +/** + * @name HPRT register bit definitions + * @{ */ #define HPRT_PrtSpd_MASK (3<<17) /**< port Speed mask. */ #define HPRT_PrtSpd_HS (0<<17) /**< High Speed value. */ -#define HPRT_PrtSpd_FS (1<<17) /**< Full Speed value. */ +#define HPRT_PrtSpd_FS (1U<<17) /**< Full Speed value. */ #define HPRT_PrtSpd_LS (2<<17) /**< Low Speed value. */ #define HPRT_PrtTstCtl_MASK (15<<13) /**< port Test control mask.*/ #define HPRT_PrtTstCtl(n) ((n)<<13) /**< port Test control value. */ -#define HPRT_PrtPwr (1<<12) /**< port Power. */ +#define HPRT_PrtPwr (1U<<12) /**< port power. */ #define HPRT_PrtLnSts_MASK (3<<11) /**< port Line status mask. */ -#define HPRT_PrtLnSts_DM (1<<11) /**< Logic level of D-. */ -#define HPRT_PrtLnSts_DP (1<<10) /**< Logic level of D+. */ -#define HPRT_PrtRst (1<<8) /**< port Reset. */ -#define HPRT_PrtSusp (1<<7) /**< port Suspend. */ -#define HPRT_PrtRes (1<<6) /**< port Resume. */ -#define HPRT_PrtOvrCurrChng (1<<5) /**< port Overcurrent - Change. */ -#define HPRT_PrtOvrCurrAct (1<<4) /**< port Overcurrent +#define HPRT_PrtLnSts_DM (1U<<11) /**< Logic level of D-. */ +#define HPRT_PrtLnSts_DP (1U<<10) /**< Logic level of D+. */ +#define HPRT_PrtRst (1U<<8) /**< port reset. */ +#define HPRT_PrtSusp (1U<<7) /**< port suspend. */ +#define HPRT_PrtRes (1U<<6) /**< port Resume. */ +#define HPRT_PrtOvrCurrChng (1U<<5) /**< port Overcurrent + change. */ +#define HPRT_PrtOvrCurrAct (1U<<4) /**< port Overcurrent Active. */ -#define HPRT_PrtEnChng (1<<3) /**< port Enable/Disable - Change. */ -#define HPRT_PrtEna (1<<2) /**< port Enable. */ -#define HPRT_PrtConnDet (1<<1) /**< port Connect Detected. */ -#define HPRT_PrtConnSts (1<<0) /**< .*/ +#define HPRT_PrtEnChng (1U<<3) /**< port enable/Disable + change. */ +#define HPRT_PrtEna (1U<<2) /**< port enable. */ +#define HPRT_PrtConnDet (1U<<1) /**< port Connect detected. */ +#define HPRT_PrtConnSts (1U<<0) /**< .*/ +/** @} */ -/* - * HCCHAR register bit definitions. +/** + * @name HCCHAR register bit definitions + * @{ */ -#define HCCHAR_ChEna (1u<<31) /**< channel Enable. */ -#define HCCHAR_ChDis (1<<30) /**< channel Disable. */ -#define HCCHAR_OddFrm (1<<29) /**< Odd frame. */ +#define HCCHAR_ChEna (1u<<31) /**< channel enable. */ +#define HCCHAR_ChDis (1U<<30) /**< channel Disable. */ +#define HCCHAR_OddFrm (1U<<29) /**< Odd frame. */ #define HCCHAR_DevAddr_MASK (0x7F<<22) /**< Device Address mask. */ #define HCCHAR_DevAddr(n) ((n)<<22) /**< Device Address value. */ -#define HCCHAR_MC_EC_MASK (3<<20) /**< Multi Count (MC) / Error - Count mask. */ -#define HCCHAR_MC_EC(n) ((n)<<20) /**< Multi Count (MC) / Error - Count value. */ +#define HCCHAR_MC_EC_MASK (3<<20) /**< Multi count (MC) / Error + count mask. */ +#define HCCHAR_MC_EC(n) ((n)<<20) /**< Multi count (MC) / Error + count value. */ #define HCCHAR_EPType_MASK (3<<18) /**< .*/ #define HCCHAR_EPType(n) ((n)<<18) /**< endpoint Type mask. */ #define HCCHAR_EPType_control (0<<18) /**< control endpoint value.*/ -#define HCCHAR_EPType_Isochronous (1<<18) /**< Isochronous endpoint +#define HCCHAR_EPType_isochronous (1U<<18) /**< isochronous endpoint value. */ #define HCCHAR_EPType_Bulk (2<<18) /**< Bulk endpoint value. */ #define HCCHAR_EPType_interrupt (3<<18) /**< interrupt endpoint value. */ -#define HCCHAR_LSpdDev (1<<17) /**< Low-Speed Device. */ -#define HCCHAR_EPDir (1<<15) /**< endpoint Direction. */ +#define HCCHAR_LSpdDev (1U<<17) /**< Low-Speed Device. */ +#define HCCHAR_EPDir (1U<<15) /**< endpoint Direction. */ #define HCCHAR_EPNum_MASK (15<<11) /**< endpoint number mask. */ #define HCCHAR_EPNum(n) ((n)<<11) /**< endpoint number value. */ #define HCCHAR_MPS_MASK (11<<0) /**< Maximum Packet size mask. */ #define HCCHAR_MPS(n) (11<<0) /**< Maximum Packet size value. */ +/** @} */ -/* - * HCSPLT register bit definitions. +/** + * @name HCSPLT register bit definitions + * @{ */ -#define HCSPLT_SpltEna (1u<<31) /**< Split Enable. */ -#define HCSPLT_CompSplt (1<<16) /**< Do Complete Split. */ +#define HCSPLT_SpltEna (1u<<31) /**< Split enable. */ +#define HCSPLT_CompSplt (1U<<16) /**< Do Complete Split. */ #define HCSPLT_XactPos_MASK (3<<14) /**< Transaction Position. */ #define HCSPLT_XactPos_Mid (0<<14) /**< Middle. */ -#define HCSPLT_XactPos_End (1<<14) /**< End. */ +#define HCSPLT_XactPos_end (1U<<14) /**< End. */ #define HCSPLT_XactPos_Begin (2<<14) /**< Begin. */ -#define HCSPLT_XactPos_all (3<<14) /**< all. */ +#define HCSPLT_XactPos_all (3<<14) /**< All. */ #define HCSPLT_HubAddr_MASK (0x7F<<6) /**< Hub Address mask. */ #define HCSPLT_HubAddr(n) ((n)<