From 72c3417c88c7133ce4e38c49e7d25befea877131 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 25 Dec 2017 16:14:03 +0000 Subject: More H7-related changes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11182 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c | 34 +++++++++++++++++++++++++++ os/hal/ports/STM32/STM32H7xx/hal_lld.c | 32 ++++++++++++++++--------- os/hal/ports/STM32/STM32H7xx/hal_lld.h | 11 +++++---- os/hal/ports/STM32/STM32H7xx/stm32_registry.h | 1 + 4 files changed, 63 insertions(+), 15 deletions(-) (limited to 'os') diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c index 85d16a375..f8ac6b761 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c @@ -158,8 +158,13 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Multiple channel setting of the same channel not allowed, first disable it. This is done because on STM32 the same channel cannot be mapped on multiple ports.*/ +#if defined(STM32_EXTI_ENHANCED) + osalDbgAssert(((EXTI->RTSR1 & padmask) == 0U) && + ((EXTI->FTSR1 & padmask) == 0U), "channel already in use"); +#else osalDbgAssert(((EXTI->RTSR & padmask) == 0U) && ((EXTI->FTSR & padmask) == 0U), "channel already in use"); +#endif /* Index and mask of the SYSCFG CR register to be used.*/ cridx = (uint32_t)pad >> 2U; @@ -174,6 +179,20 @@ void _pal_lld_enablepadevent(ioportid_t port, SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff); /* Programming edge registers.*/ +#if defined(STM32_EXTI_ENHANCED) + if (mode & PAL_EVENT_MODE_RISING_EDGE) + EXTI->RTSR1 |= padmask; + else + EXTI->RTSR1 &= ~padmask; + if (mode & PAL_EVENT_MODE_FALLING_EDGE) + EXTI->FTSR1 |= padmask; + else + EXTI->FTSR1 &= ~padmask; + + /* Programming interrupt and event registers.*/ + EXTI_D1->IMR1 |= padmask; + EXTI_D1->EMR1 &= ~padmask; +#else if (mode & PAL_EVENT_MODE_RISING_EDGE) EXTI->RTSR |= padmask; else @@ -186,6 +205,7 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Programming interrupt and event registers.*/ EXTI->IMR |= padmask; EXTI->EMR &= ~padmask; +#endif } /** @@ -200,8 +220,13 @@ void _pal_lld_enablepadevent(ioportid_t port, void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { uint32_t padmask, rtsr1, ftsr1; +#if defined(STM32_EXTI_ENHANCED) + rtsr1 = EXTI->RTSR1; + ftsr1 = EXTI->FTSR1; +#else rtsr1 = EXTI->RTSR; ftsr1 = EXTI->FTSR; +#endif /* Mask of the pad.*/ padmask = 1U << (uint32_t)pad; @@ -222,12 +247,21 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { osalDbgAssert(crport == portidx, "channel mapped on different port"); +#if defined(STM32_EXTI_ENHANCED) + /* Disabling channel.*/ + EXTI_D1->IMR1 &= ~padmask; + EXTI_D1->EMR1 &= ~padmask; + EXTI->RTSR1 = rtsr1 & ~padmask; + EXTI->FTSR1 = ftsr1 & ~padmask; + EXTI_D1->PR1 = padmask; +#else /* Disabling channel.*/ EXTI->IMR &= ~padmask; EXTI->EMR &= ~padmask; EXTI->RTSR = rtsr1 & ~padmask; EXTI->FTSR = ftsr1 & ~padmask; EXTI->PR = padmask; +#endif #if PAL_USE_CALLBACKS || PAL_USE_WAIT /* Callback cleared and/or thread reset.*/ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index ef8a6fae9..e39f06ec2 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -36,7 +36,7 @@ * @brief CMSIS system core clock variable. * @note It is declared in system_stm32f7xx.h. */ -uint32_t SystemCoreClock = STM32_HCLK; +uint32_t SystemCoreClock = STM32_C_CK; /*===========================================================================*/ /* Driver local variables and types. */ @@ -92,23 +92,22 @@ static inline void init_bkp_domain(void) { * @brief Initializes the PWR unit. */ static inline void init_pwr(void) { +#if 0 + PWR_TypeDef *pwr = PWR; /* For inspection.*/ + (void)pwr; +#endif - PWR->CR1 = STM32_PWR_CR1; + PWR->CR1 = STM32_PWR_CR1 | 0xF0000000; PWR->CR2 = STM32_PWR_CR2; PWR->CR3 = STM32_PWR_CR3; - PWR->CR1 = STM32_PWR_CR1; PWR->CPUCR = STM32_PWR_CPUCR; PWR->D3CR = STM32_VOS; while ((PWR->CSR1 & PWR_CSR1_ACTVOS) == 0) ; #if STM32_PWR_CR2 & PWR_CR2_BREN - while ((PWR->CR2 & PWR_CR2_BRRDY) == 0) - ; - rccEnableBKPRAM(false); -#endif -#if STM32_PWR_CR3 & PWR_CR3_USB33DEN - while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0) - ; +// while ((PWR->CR2 & PWR_CR2_BRRDY) == 0) +// ; +// rccEnableBKPRAM(false); #endif } @@ -158,8 +157,19 @@ void hal_lld_init(void) { * @special */ void stm32_clock_init(void) { +#if 0 + RCC_TypeDef *rcc = RCC; /* For inspection.*/ + (void)rcc; +#endif #if STM32_NO_INIT == FALSE +#if !defined(STM32_DISABLE_ERRATA_2_2_15) + /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data + read corruption. + AXI->TARG7_FN_MOD.*/ + *((volatile uint32_t *)0x51000000 + 0x1108 + 0x7000) = 0x00000001U; +#endif + /* PWR initialization.*/ init_pwr(); @@ -326,7 +336,7 @@ void stm32_clock_init(void) { from HSI.*/ #if STM32_SW != STM32_SW_HSI_CK RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 3U)) ; #endif diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index e29b9423d..9f9818f18 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -538,8 +538,7 @@ * @brief PWR CR1 initializer. */ #if !defined(STM32_PWR_CR1) || defined(__DOXYGEN__) -#define STM32_PWR_CR1 (PWR_CR1_PVDEN | \ - PWR_CR1_SVOS_1 | \ +#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | \ PWR_CR1_SVOS_0) #endif @@ -554,8 +553,7 @@ * @brief PWR CR3 initializer. */ #if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__) -#define STM32_PWR_CR3 (PWR_CR3_SCUEN | \ - PWR_CR3_LDOEN | \ +#define STM32_PWR_CR3 (PWR_CR3_LDOEN | \ PWR_CR3_USBREGEN | \ PWR_CR3_USB33DEN) #endif @@ -2068,6 +2066,11 @@ #error "invalid STM32_D1CPRE value specified" #endif +/** + * @brief Core clock. + */ +#define STM32_C_CK STM32_SYS_D1CPRE_CK + /** * @brief HCLK clock. */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index df64d5a39..b615d32e4 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -77,6 +77,7 @@ #define STM32_ETH_NUMBER 61 /* EXTI attributes.*/ +#define STM32_EXTI_ENHANCED /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE -- cgit v1.2.3