From 6ae531cde4660cff8217f96fa621306efdeea207 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 21 May 2012 16:59:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4225 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/LPC11Uxx/gpt_lld.c | 342 +++++++++++++++++++++++++ os/hal/platforms/LPC11Uxx/gpt_lld.h | 208 +++++++++++++++ os/hal/platforms/LPC11Uxx/hal_lld.c | 8 +- os/hal/platforms/LPC11Uxx/hal_lld.h | 4 +- os/hal/platforms/LPC11Uxx/platform.mk | 2 + os/hal/platforms/LPC11Uxx/serial_lld.c | 20 +- os/hal/platforms/LPC11Uxx/spi_lld.c | 395 +++++++++++++++++++++++++++++ os/hal/platforms/LPC11Uxx/spi_lld.h | 315 +++++++++++++++++++++++ os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld | 4 +- os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld | 151 +++++++++++ os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld | 4 +- 11 files changed, 1430 insertions(+), 23 deletions(-) create mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.c create mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.h create mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.c create mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.h create mode 100644 os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld (limited to 'os') diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.c b/os/hal/platforms/LPC11Uxx/gpt_lld.c new file mode 100644 index 000000000..0d3963f78 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.c @@ -0,0 +1,342 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/gpt_lld.c + * @brief LPC11Uxx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B0 */ + +#if LPC_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_CT16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_CT16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_CT32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_CT32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.h b/os/hal/platforms/LPC11Uxx/gpt_lld.h new file mode 100644 index 000000000..e8d347b09 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/gpt_lld.h + * @brief LPC11Uxx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC_GPT_USE_CT16B0 && !LPC_GPT_USE_CT16B1 && \ + !LPC_GPT_USE_CT32B0 && !LPC_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_CTxxBx_Type *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c index 9b1fac622..fa33511fe 100644 --- a/os/hal/platforms/LPC11Uxx/hal_lld.c +++ b/os/hal/platforms/LPC11Uxx/hal_lld.c @@ -29,11 +29,6 @@ #include "ch.h" #include "hal.h" -/** - * @brief Register missing in NXP header file. - */ -#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -81,7 +76,8 @@ void lpc_clock_init(void) { unsigned i; /* Flash wait states setting, the code takes care to not touch TBD bits.*/ - FLASHCFG = (FLASHCFG & ~3) | LPC_FLASHCFG_FLASHTIM; + LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~3) | + LPC_FLASHCFG_FLASHTIM; /* System oscillator initialization if required.*/ #if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.h b/os/hal/platforms/LPC11Uxx/hal_lld.h index a544dfa9a..2f2347ef2 100644 --- a/os/hal/platforms/LPC11Uxx/hal_lld.h +++ b/os/hal/platforms/LPC11Uxx/hal_lld.h @@ -109,7 +109,7 @@ /** * @brief Calculated SYSOSCCTRL setting. */ -#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__) #define LPC_SYSOSCCTRL 0 #else #define LPC_SYSOSCCTRL 1 @@ -212,7 +212,7 @@ extern "C" { #endif void hal_lld_init(void); - void lpc111x_clock_init(void); + void lpc_clock_init(void); #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/LPC11Uxx/platform.mk b/os/hal/platforms/LPC11Uxx/platform.mk index 3dc47e897..45495ec46 100644 --- a/os/hal/platforms/LPC11Uxx/platform.mk +++ b/os/hal/platforms/LPC11Uxx/platform.mk @@ -1,6 +1,8 @@ # List of all the LPC11Uxx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC11Uxx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC11Uxx/serial_lld.c # Required include directories diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.c b/os/hal/platforms/LPC11Uxx/serial_lld.c index 4463a15ad..03bc9bbf9 100644 --- a/os/hal/platforms/LPC11Uxx/serial_lld.c +++ b/os/hal/platforms/LPC11Uxx/serial_lld.c @@ -56,13 +56,13 @@ static const SerialConfig default_config = { /*===========================================================================*/ /** - * @brief UART initialization. + * @brief USART initialization. * - * @param[in] sdp communication channel associated to the UART + * @param[in] sdp communication channel associated to the USART * @param[in] config the architecture-dependent serial driver configuration */ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; uint32_t div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4); u->LCR = config->sc_lcr | LCR_DLAB; @@ -77,11 +77,11 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { } /** - * @brief UART de-initialization. + * @brief USART de-initialization. * - * @param[in] u pointer to an UART I/O block + * @param[in] u pointer to an USART I/O block */ -static void uart_deinit(LPC_UART_TypeDef *u) { +static void uart_deinit(LPC_USART_Type *u) { u->LCR = LCR_DLAB; u->DLL = 1; @@ -126,7 +126,7 @@ static void set_error(SerialDriver *sdp, IOREG32 err) { * @param[in] sdp communication channel associated to the UART */ static void serve_interrupt(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; while (TRUE) { switch (u->IIR & IIR_SRC_MASK) { @@ -179,7 +179,7 @@ static void serve_interrupt(SerialDriver *sdp) { * @brief Attempts a TX FIFO preload. */ static void preload(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; if (u->LSR & LSR_THRE) { int i = LPC_SERIAL_FIFO_PRELOAD; @@ -239,9 +239,7 @@ void sd_lld_init(void) { #if LPC_SERIAL_USE_UART0 sdObjectInit(&SD1, NULL, notify1); - SD1.uart = LPC_UART; - LPC_IOCON->PIO0_18 = 0x81; /* RDX without resistors. */ - LPC_IOCON->PIO0_19 = 0x81; /* TDX without resistors. */ + SD1.uart = LPC_USART; #endif } diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.c b/os/hal/platforms/LPC11Uxx/spi_lld.c new file mode 100644 index 000000000..49fcf1913 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.c @@ -0,0 +1,395 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/spi_lld.c + * @brief LPC11Uxx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ? + LPC_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; +#endif /* LPC_SPI_USE_SSP0 */ + +#if LPC_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; +#endif /* LPC_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.h b/os/hal/platforms/LPC11Uxx/spi_lld.h new file mode 100644 index 000000000..2cd018406 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.h @@ -0,0 +1,315 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/spi_lld.h + * @brief LPC11Uxx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP1 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC_SPI_SSP0CLKDIV < 1) || (LPC_SPI_SSP0CLKDIV > 255) +#error "invalid LPC_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC_SPI_SSP1CLKDIV < 1) || (LPC_SPI_SSP1CLKDIV > 255) +#error "invalid LPC_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC_SPI_SSP0_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC_SPI_SSP1_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSPx_Type *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld index c4f328a15..214cd3feb 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld @@ -21,8 +21,8 @@ /* * LPC1114 memory setup. */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0200; +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; MEMORY { diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld new file mode 100644 index 000000000..4f7b3839c --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld @@ -0,0 +1,151 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC11U14 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 4k + usbram : org = 0x20004000, len = 2k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld index 4431d7a75..4e801eae9 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld +++ b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld @@ -21,8 +21,8 @@ /* * LPC1343 memory setup. */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0200; +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; MEMORY { -- cgit v1.2.3