From 633098ebcd87d2a654deede6feff0d93fdabaebc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 6 Dec 2012 10:53:16 +0000 Subject: STM32F3 SPI working, STM32F0 support update. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4879 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/GPIOv2/pal_lld.h | 5 ++++- os/hal/platforms/STM32F0xx/hal_lld.c | 20 +++++++++-------- os/hal/platforms/STM32F0xx/hal_lld.h | 40 ++++++++++++++++++--------------- 3 files changed, 37 insertions(+), 28 deletions(-) (limited to 'os') diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.h b/os/hal/platforms/STM32/GPIOv2/pal_lld.h index 93eac7889..d00180461 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.h +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.h @@ -59,10 +59,13 @@ #define PAL_STM32_OTYPE_OPENDRAIN (1 << 2) #define PAL_STM32_OSPEED_MASK (3 << 3) -/* TODO: F0 and F3 are different from F2/F4 here.*/ #define PAL_STM32_OSPEED_LOWEST (0 << 3) +#if defined(STM32F0XX) || defined(STM32F30X) +#define PAL_STM32_OSPEED_MID (1 << 3) +#else #define PAL_STM32_OSPEED_MID1 (1 << 3) #define PAL_STM32_OSPEED_MID2 (2 << 3) +#endif #define PAL_STM32_OSPEED_HIGHEST (3 << 3) #define PAL_STM32_PUDR_MASK (3 << 5) diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 10b6db940..57b548ce3 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -29,10 +29,6 @@ #include "ch.h" #include "hal.h" -/* TODO: LSEBYP like in F3.*/ -/* TODO: LSEDRV like in F3.*/ -/* TODO: PREDIV like in F3.*/ - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -64,7 +60,13 @@ static void hal_lld_backup_domain_init(void) { /* If enabled then the LSE is started.*/ #if STM32_LSE_ENABLED - RCC->BDCR |= RCC_BDCR_LSEON; +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; +#endif while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) ; /* Waits until LSE is stable. */ #endif @@ -172,10 +174,10 @@ void stm32_clock_init(void) { #endif /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE | - STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | - STM32_HPRE; - RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | + RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE | STM32_HPRE; + RCC->CFGR2 = STM32_PREDIV; + RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW; #if STM32_ACTIVATE_PLL diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index d38248ce5..775892391 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -24,6 +24,8 @@ * @pre This module requires the following macros to be defined in the * @p board.h file: * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). * - STM32_HSECLK. * - STM32_HSE_BYPASS (optionally). * . @@ -170,9 +172,6 @@ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */ -#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */ -#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */ - #define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */ #define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */ #define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */ @@ -506,11 +505,11 @@ * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the * system clock source. - * @note The default value is calculated for a 48MHz system clock from + * @note The default value is calculated for a 72MHz system clock from * a 8MHz crystal using the PLL. */ -#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__) -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__) +#define STM32_PREDIV_VALUE 1 #endif /** @@ -704,6 +703,18 @@ #error "LSE frequency not defined" #endif +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + #if STM32_CECSW == STM32_CECSW_LSE #error "LSE not enabled, required by STM32_CECSW" #endif @@ -712,10 +723,6 @@ #error "LSE not enabled, required by STM32_USART1SW" #endif -#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) -#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" -#endif - #else /* !STM32_LSE_ENABLED */ #if STM32_RTCSEL == STM32_RTCSEL_LSE @@ -737,9 +744,10 @@ #endif /* HSE prescaler setting check.*/ -#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \ - (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2) -#error "invalid STM32_PLLXTPRE value specified" +#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16)) +#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0) +#else +#error "invalid STM32_PREDIV value specified" #endif /** @@ -756,11 +764,7 @@ * @brief PLL input clock frequency. */ #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) -#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKIN (STM32_HSECLK / 1) -#else -#define STM32_PLLCLKIN (STM32_HSECLK / 2) -#endif +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE) #elif STM32_PLLSRC == STM32_PLLSRC_HSI #define STM32_PLLCLKIN (STM32_HSICLK / 2) #else -- cgit v1.2.3