From 40823c9995b66157706d0cea29646525ddf62978 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Oct 2014 20:29:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7399 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/rt/ports/ARM/compilers/GCC/chcoreasm.s | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'os') diff --git a/os/rt/ports/ARM/compilers/GCC/chcoreasm.s b/os/rt/ports/ARM/compilers/GCC/chcoreasm.s index 7ab661443..421fd271f 100644 --- a/os/rt/ports/ARM/compilers/GCC/chcoreasm.s +++ b/os/rt/ports/ARM/compilers/GCC/chcoreasm.s @@ -140,9 +140,9 @@ _port_switch_arm: /* * Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address - * of a register holding the address of the ISR to be invoked, the IRS will - * then return in the common epilogue code where the context switch will - * be performed if required. + * of a register holding the address of the ISR to be invoked, the ISR + * then returns in the common epilogue code where the context switch will + * be performed, if required. */ .code 32 .func -- cgit v1.2.3