From 1ddf1e6ac0f3b0cd03031c6821c919f9a5b3bd74 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Sun, 20 Nov 2016 20:53:25 +0000 Subject: Added support for STM32F412. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9936 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld | 85 +++ .../startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld | 85 +++ os/hal/ports/STM32/STM32F4xx/hal_lld.h | 66 +-- os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 613 ++++++++++++++++----- 4 files changed, 669 insertions(+), 180 deletions(-) create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld (limited to 'os') diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld new file mode 100644 index 000000000..713a912d6 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xE.ld @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F412xE memory setup. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 512k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld new file mode 100644 index 000000000..0f82307af --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F412xG.ld @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F412xG memory setup. + */ +MEMORY +{ + flash0 : org = 0x08000000, len = 1M + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 256k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 9a71b6c34..e9ce800b4 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -61,41 +61,38 @@ #if defined(STM32F205xx) || defined(__DOXYGEN__) #define PLATFORM_NAME "STM32F205 High Performance" -#elif defined(STM32F215xx) -#define PLATFORM_NAME "STM32F215 High Performance" - #elif defined(STM32F207xx) #define PLATFORM_NAME "STM32F207 High Performance" +#elif defined(STM32F215xx) +#define PLATFORM_NAME "STM32F215 High Performance" + #elif defined(STM32F217xx) #define PLATFORM_NAME "STM32F217 High Performance" -#elif defined(STM32F401xC) -#define PLATFORM_NAME "STM32F401xC High Performance with DSP and FPU" - -#elif defined(STM32F401xE) -#define PLATFORM_NAME "STM32F401xE High Performance with DSP and FPU" +#elif defined(STM32F401xx) +#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU" #elif defined(STM32F405xx) #define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU" -#elif defined(STM32F415xx) -#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU" - #elif defined(STM32F407xx) #define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU" -#elif defined(STM32F417xx) -#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU" +#elif defined(STM32F410xx) +#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU" -#elif defined(STM32F410Cx) -#define PLATFORM_NAME "STM32F410Cx High Performance with DSP and FPU" +#elif defined(STM32F411xx) +#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU" -#elif defined(STM32F410Rx) -#define PLATFORM_NAME "STM32F410Rx High Performance with DSP and FPU" +#elif defined(STM32F412xx) +#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU" + +#elif defined(STM32F415xx) +#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU" -#elif defined(STM32F411xE) -#define PLATFORM_NAME "STM32F411xE High Performance with DSP and FPU" +#elif defined(STM32F417xx) +#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU" #elif defined(STM32F427xx) #define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU" @@ -226,7 +223,7 @@ #define STM32_SPII2S_MAX 45000000 #endif -#if defined(STM32F40_41xxx) || defined(__DOXYGEN__) +#if defined(STM32F40_41xxx) #define STM32_SYSCLK_MAX 168000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -246,7 +243,7 @@ #define STM32_SPII2S_MAX 42000000 #endif -#if defined(STM32F401xx) || defined(__DOXYGEN__) +#if defined(STM32F401xx) #define STM32_SYSCLK_MAX 84000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -266,7 +263,8 @@ #define STM32_SPII2S_MAX 42000000 #endif -#if defined(STM32F410xx) || defined(__DOXYGEN__) +#if defined(STM32F410xx) || defined(STM32F411xx) || \ + defined(STM32F412xx) #define STM32_SYSCLK_MAX 100000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -286,27 +284,7 @@ #define STM32_SPII2S_MAX 50000000 #endif -#if defined(STM32F411xx) || defined(__DOXYGEN__) -#define STM32_SYSCLK_MAX 100000000 -#define STM32_HSECLK_MAX 26000000 -#define STM32_HSECLK_BYP_MAX 50000000 -#define STM32_HSECLK_MIN 4000000 -#define STM32_HSECLK_BYP_MIN 1000000 -#define STM32_LSECLK_MAX 32768 -#define STM32_LSECLK_BYP_MAX 1000000 -#define STM32_LSECLK_MIN 32768 -#define STM32_PLLIN_MAX 2100000 -#define STM32_PLLIN_MIN 950000 -#define STM32_PLLVCO_MAX 432000000 -#define STM32_PLLVCO_MIN 100000000 -#define STM32_PLLOUT_MAX 100000000 -#define STM32_PLLOUT_MIN 24000000 -#define STM32_PCLK1_MAX 50000000 -#define STM32_PCLK2_MAX 100000000 -#define STM32_SPII2S_MAX 50000000 -#endif - -#if defined(STM32F446xx) || defined(__DOXYGEN__) +#if defined(STM32F446xx) #define STM32_SYSCLK_MAX 180000000 #define STM32_HSECLK_MAX 26000000 #define STM32_HSECLK_BYP_MAX 50000000 @@ -1462,7 +1440,7 @@ #endif #define STM32_OVERDRIVE_REQUIRED FALSE -#elif defined(STM32F410xx) || defined(STM32F411xx) +#elif defined(STM32F410xx) || defined(STM32F411xx) || defined(STM32F412xx) #if STM32_SYSCLK <= 64000000 #define STM32_VOS STM32_VOS_SCALE3 #elif STM32_SYSCLK <= 84000000 diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 3e708d980..159a911c0 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -40,22 +40,27 @@ #define STM32F427_437xx #define STM32F4XX -#elif defined(STM32F405xx) || defined(STM32F415xx) || \ - defined(STM32F407xx) || defined(STM32F417xx) -#define STM32F40_41xxx +#elif defined(STM32F412Cx) || defined(STM32F412Rx) || \ + defined(STM32F412Vx) || defined(STM32F412Zx) +#define STM32F412xx #define STM32F4XX -#elif defined(STM32F401xC) || defined(STM32F401xE) -#define STM32F401xx +#elif defined(STM32F411xE) +#define STM32F411xx #define STM32F4XX -#elif defined(STM32F410Cx) || defined(STM32F410Rx) -#define STM32F410C_410Rx +#elif defined(STM32F410Cx) || defined(STM32F410Rx) || \ + defined(STM32F410Tx) #define STM32F410xx #define STM32F4XX -#elif defined(STM32F411xE) -#define STM32F411xx +#elif defined(STM32F405xx) || defined(STM32F415xx) || \ + defined(STM32F407xx) || defined(STM32F417xx) +#define STM32F40_41xxx +#define STM32F4XX + +#elif defined(STM32F401xC) || defined(STM32F401xE) +#define STM32F401xx #define STM32F4XX #elif defined(STM32F205xx) || defined(STM32F215xx) || \ @@ -78,7 +83,9 @@ /*===========================================================================*/ /* STM32F469xx, STM32F479xx. */ /*===========================================================================*/ -#if defined(STM32F469_479xx) + +#if defined(STM32F469_479xx) || defined(__DOXYGEN__) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -446,7 +453,9 @@ /*===========================================================================*/ /* STM32F446xx. */ /*===========================================================================*/ + #if defined(STM32F446xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -789,8 +798,9 @@ /*===========================================================================*/ /* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */ /*===========================================================================*/ -#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \ - defined(__DOXYGEN__) + +#if defined(STM32F429_439xx) || defined(STM32F427_437xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -1152,10 +1162,11 @@ #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */ /*===========================================================================*/ -/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */ -/* STM32F215xx, STM32F207xx, STM32F217xx. */ +/* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx */ /*===========================================================================*/ -#if defined(STM32F40_41xxx) || defined(STM32F2XX) + +#if defined(STM32F412xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -1165,16 +1176,8 @@ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC1_DMA_CHN 0x00000000 -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_SDADC1 FALSE @@ -1187,14 +1190,8 @@ #define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_DAC1_CH1_DMA_CHN 0x00700000 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_DAC1_CH2_DMA_CHN 0x07000000 - +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE @@ -1239,14 +1236,7 @@ #define STM32_DMA2_CH7_NUMBER 70 /* ETH attributes.*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \ - defined(STM32F215xx) #define STM32_HAS_ETH FALSE -#else -#define STM32_HAS_ETH TRUE -#define STM32_ETH_HANDLER Vector134 -#define STM32_ETH_NUMBER 61 -#endif /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 23 @@ -1261,7 +1251,7 @@ #define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ @@ -1271,8 +1261,7 @@ RCC_AHB1ENR_GPIOEEN | \ RCC_AHB1ENR_GPIOFEN | \ RCC_AHB1ENR_GPIOGEN | \ - RCC_AHB1ENR_GPIOHEN | \ - RCC_AHB1ENR_GPIOIEN) + RCC_AHB1ENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE @@ -1299,15 +1288,15 @@ #define STM32_HAS_I2C4 FALSE /* QUADSPI attributes.*/ -#define STM32_HAS_QUADSPI1 FALSE +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_HANDLER Vector1B0 +#define STM32_QUADSPI1_NUMBER 92 +#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_QUADSPI1_DMA_CHN 0x30000000 /* RTC attributes.*/ #define STM32_HAS_RTC TRUE -#if !defined(STM32F2XX) #define STM32_RTC_HAS_SUBSECONDS TRUE -#else -#define STM32_RTC_HAS_SUBSECONDS FALSE -#endif #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_HAS_INTERRUPTS FALSE @@ -1346,8 +1335,26 @@ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_SPI3_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI4 FALSE -#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3))|\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_RX_DMA_CHN 0x00045004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 5))|\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07520000 + #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ @@ -1381,10 +1388,6 @@ #define STM32_TIM7_IS_32BITS FALSE #define STM32_TIM7_CHANNELS 0 -#define STM32_HAS_TIM8 TRUE -#define STM32_TIM8_IS_32BITS FALSE -#define STM32_TIM8_CHANNELS 6 - #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 @@ -1403,12 +1406,13 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 +#define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE @@ -1433,24 +1437,12 @@ #define STM32_USART2_TX_DMA_CHN 0x04000000 #define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) #define STM32_USART3_RX_DMA_CHN 0x00000040 #define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 4)) #define STM32_USART3_TX_DMA_CHN 0x00074000 -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_UART4_RX_DMA_CHN 0x00000400 -#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_UART4_TX_DMA_CHN 0x00040000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) -#define STM32_UART5_RX_DMA_CHN 0x00000004 -#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_UART5_TX_DMA_CHN 0x40000000 - #define STM32_HAS_USART6 TRUE #define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2)) @@ -1459,6 +1451,8 @@ STM32_DMA_STREAM_ID_MSK(2, 7)) #define STM32_USART6_TX_DMA_CHN 0x55000000 +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE @@ -1466,10 +1460,9 @@ /* USB attributes.*/ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE -#define STM32_OTG1_ENDPOINTS 3 -#define STM32_HAS_OTG2 TRUE -#define STM32_OTG2_ENDPOINTS 5 +#define STM32_OTG1_ENDPOINTS 4 +#define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB FALSE /* IWDG attributes.*/ @@ -1483,19 +1476,20 @@ #define STM32_HAS_DMA2D FALSE /* FSMC attributes.*/ -#define STM32_HAS_FSMC TRUE -#define STM32_FSMC_IS_FMC FALSE +#define STM32_HAS_FSMC FALSE /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */ +#endif /* defined(STM32F412xx) */ /*===========================================================================*/ -/* STM32F401xx. */ +/* STM32F411xC, STM32F411xE */ /*===========================================================================*/ -#if defined(STM32F401xx) + +#if defined(STM32F411xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -1505,16 +1499,8 @@ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC1_DMA_CHN 0x00000000 -#define STM32_HAS_ADC2 TRUE -#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_ADC2_DMA_CHN 0x00001100 - -#define STM32_HAS_ADC3 TRUE -#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 1)) -#define STM32_ADC3_DMA_CHN 0x00000022 - +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE #define STM32_HAS_ADC4 FALSE #define STM32_HAS_SDADC1 FALSE @@ -1522,9 +1508,8 @@ #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 FALSE @@ -1595,7 +1580,8 @@ RCC_AHB1ENR_GPIOBEN | \ RCC_AHB1ENR_GPIOCEN | \ RCC_AHB1ENR_GPIODEN | \ - RCC_AHB1ENR_GPIOEEN) + RCC_AHB1ENR_GPIOEEN | \ + RCC_AHB1ENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE @@ -1674,7 +1660,15 @@ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_SPI4_TX_DMA_CHN 0x00050040 -#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE +#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI5_RX_DMA_CHN 0x00702000 +#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SPI5_TX_DMA_CHN 0x07020000 + #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ @@ -1761,8 +1755,8 @@ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE #define STM32_OTG1_ENDPOINTS 4 -#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_OTG2 FALSE #define STM32_HAS_USB FALSE /* IWDG attributes.*/ @@ -1782,12 +1776,14 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -#endif /* defined(STM32F401xx) */ +#endif /* defined(STM32F411xx) */ /*===========================================================================*/ /* STM32F410Cx, STM32F410Rx. */ /*===========================================================================*/ -#if defined(STM32F410C_410Rx) + +#if defined(STM32F410xx) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -2046,12 +2042,15 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -#endif /* defined(STM32F410C_410Rx) */ +#endif /* defined(STM32F410xx) */ /*===========================================================================*/ -/* STM32F411xE. */ +/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F205xx */ +/* STM32F215xx, STM32F207xx, STM32F217xx. */ /*===========================================================================*/ -#if defined(STM32F411xx) + +#if defined(STM32F40_41xxx) || defined(STM32F2XX) + /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 @@ -2061,8 +2060,16 @@ STM32_DMA_STREAM_ID_MSK(2, 4)) #define STM32_ADC1_DMA_CHN 0x00000000 -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + #define STM32_HAS_ADC4 FALSE #define STM32_HAS_SDADC1 FALSE @@ -2070,12 +2077,19 @@ #define STM32_HAS_SDADC3 FALSE /* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_DAC1_CH1_DMA_CHN 0x00700000 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_DAC1_CH2_DMA_CHN 0x07000000 + #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE @@ -2120,7 +2134,14 @@ #define STM32_DMA2_CH7_NUMBER 70 /* ETH attributes.*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F205xx) || \ + defined(STM32F215xx) #define STM32_HAS_ETH FALSE +#else +#define STM32_HAS_ETH TRUE +#define STM32_ETH_HANDLER Vector134 +#define STM32_ETH_NUMBER 61 +#endif /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 23 @@ -2133,9 +2154,9 @@ #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOH TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI TRUE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE #define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ @@ -2143,7 +2164,10 @@ RCC_AHB1ENR_GPIOCEN | \ RCC_AHB1ENR_GPIODEN | \ RCC_AHB1ENR_GPIOEEN | \ - RCC_AHB1ENR_GPIOHEN) + RCC_AHB1ENR_GPIOFEN | \ + RCC_AHB1ENR_GPIOGEN | \ + RCC_AHB1ENR_GPIOHEN | \ + RCC_AHB1ENR_GPIOIEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE @@ -2174,7 +2198,11 @@ /* RTC attributes.*/ #define STM32_HAS_RTC TRUE +#if !defined(STM32F2XX) #define STM32_RTC_HAS_SUBSECONDS TRUE +#else +#define STM32_RTC_HAS_SUBSECONDS FALSE +#endif #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_HAS_INTERRUPTS FALSE @@ -2213,24 +2241,8 @@ STM32_DMA_STREAM_ID_MSK(1, 7)) #define STM32_SPI3_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI4 TRUE -#define STM32_SPI4_SUPPORTS_I2S FALSE -#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ - STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_SPI4_RX_DMA_CHN 0x00005004 -#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ - STM32_DMA_STREAM_ID_MSK(2, 4)) -#define STM32_SPI4_TX_DMA_CHN 0x00050040 - -#define STM32_HAS_SPI5 TRUE -#define STM32_SPI5_SUPPORTS_I2S FALSE -#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ - STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_SPI5_RX_DMA_CHN 0x00702000 -#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\ - STM32_DMA_STREAM_ID_MSK(2, 6)) -#define STM32_SPI5_TX_DMA_CHN 0x07020000 - +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE /* TIM attributes.*/ @@ -2256,6 +2268,18 @@ #define STM32_TIM5_IS_32BITS TRUE #define STM32_TIM5_CHANNELS 4 +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + #define STM32_HAS_TIM9 TRUE #define STM32_TIM9_IS_32BITS FALSE #define STM32_TIM9_CHANNELS 2 @@ -2268,14 +2292,331 @@ #define STM32_TIM11_IS_32BITS FALSE #define STM32_TIM11_CHANNELS 2 -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 2 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 2 + +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_USART1_RX_DMA_CHN 0x00400400 +#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7) +#define STM32_USART1_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00400000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART2_TX_DMA_CHN 0x04000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1) +#define STM32_USART3_RX_DMA_CHN 0x00000040 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x00074000 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_UART4_RX_DMA_CHN 0x00000400 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_UART4_TX_DMA_CHN 0x00040000 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0) +#define STM32_UART5_RX_DMA_CHN 0x00000004 +#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART5_TX_DMA_CHN 0x40000000 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_USART6_RX_DMA_CHN 0x00000550 +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART6_TX_DMA_CHN 0x55000000 + +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 1 +#define STM32_HAS_OTG1 TRUE +#define STM32_OTG1_ENDPOINTS 3 +#define STM32_HAS_OTG2 TRUE +#define STM32_OTG2_ENDPOINTS 5 + +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED FALSE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */ + +/*===========================================================================*/ +/* STM32F401xx. */ +/*===========================================================================*/ + +#if defined(STM32F401xx) + +/* ADC attributes.*/ +#define STM32_ADC_HANDLER Vector88 +#define STM32_ADC_NUMBER 18 + +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 TRUE +#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC2_DMA_CHN 0x00001100 + +#define STM32_HAS_ADC3 TRUE +#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_ADC3_DMA_CHN 0x00000022 + +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 TRUE +#define STM32_CAN_MAX_FILTERS 28 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_CACHE_HANDLING FALSE + +#define STM32_HAS_DMA1 TRUE +#define STM32_DMA1_CH0_HANDLER Vector6C +#define STM32_DMA1_CH1_HANDLER Vector70 +#define STM32_DMA1_CH2_HANDLER Vector74 +#define STM32_DMA1_CH3_HANDLER Vector78 +#define STM32_DMA1_CH4_HANDLER Vector7C +#define STM32_DMA1_CH5_HANDLER Vector80 +#define STM32_DMA1_CH6_HANDLER Vector84 +#define STM32_DMA1_CH7_HANDLER VectorFC +#define STM32_DMA1_CH0_NUMBER 11 +#define STM32_DMA1_CH1_NUMBER 12 +#define STM32_DMA1_CH2_NUMBER 13 +#define STM32_DMA1_CH3_NUMBER 14 +#define STM32_DMA1_CH4_NUMBER 15 +#define STM32_DMA1_CH5_NUMBER 16 +#define STM32_DMA1_CH6_NUMBER 17 +#define STM32_DMA1_CH7_NUMBER 47 + +#define STM32_HAS_DMA2 TRUE +#define STM32_DMA2_CH0_HANDLER Vector120 +#define STM32_DMA2_CH1_HANDLER Vector124 +#define STM32_DMA2_CH2_HANDLER Vector128 +#define STM32_DMA2_CH3_HANDLER Vector12C +#define STM32_DMA2_CH4_HANDLER Vector130 +#define STM32_DMA2_CH5_HANDLER Vector150 +#define STM32_DMA2_CH6_HANDLER Vector154 +#define STM32_DMA2_CH7_HANDLER Vector158 +#define STM32_DMA2_CH0_NUMBER 56 +#define STM32_DMA2_CH1_NUMBER 57 +#define STM32_DMA2_CH2_NUMBER 58 +#define STM32_DMA2_CH3_NUMBER 59 +#define STM32_DMA2_CH4_NUMBER 60 +#define STM32_DMA2_CH5_NUMBER 68 +#define STM32_DMA2_CH6_NUMBER 69 +#define STM32_DMA2_CH7_NUMBER 70 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 23 +#define STM32_EXTI_IMR_MASK 0x00000000U + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \ + RCC_AHB1ENR_GPIOBEN | \ + RCC_AHB1ENR_GPIOCEN | \ + RCC_AHB1ENR_GPIODEN | \ + RCC_AHB1ENR_GPIOEEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C1_RX_DMA_CHN 0x00100001 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x11000000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C2_RX_DMA_CHN 0x00007700 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_I2C2_TX_DMA_CHN 0x70000000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C3_TX_DMA_CHN 0x00030000 + +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO TRUE +#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_SDC_SDIO_DMA_CHN 0x04004000 + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI1_RX_DMA_CHN 0x00000303 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_SPI1_TX_DMA_CHN 0x00303000 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_SPI3_RX_DMA_CHN 0x00000000 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI3_TX_DMA_CHN 0x00000000 + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI4_RX_DMA_CHN 0x00005004 +#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI4_TX_DMA_CHN 0x00050040 + +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 4 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM9 TRUE +#define STM32_TIM9_IS_32BITS FALSE +#define STM32_TIM9_CHANNELS 2 + +#define STM32_HAS_TIM10 TRUE +#define STM32_TIM10_IS_32BITS FALSE +#define STM32_TIM10_CHANNELS 2 + +#define STM32_HAS_TIM11 TRUE +#define STM32_TIM11_IS_32BITS FALSE +#define STM32_TIM11_CHANNELS 2 + +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE @@ -2317,8 +2658,8 @@ #define STM32_OTG_STEPPING 1 #define STM32_HAS_OTG1 TRUE #define STM32_OTG1_ENDPOINTS 4 - #define STM32_HAS_OTG2 FALSE + #define STM32_HAS_USB FALSE /* IWDG attributes.*/ @@ -2338,7 +2679,7 @@ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE FALSE -#endif /* defined(STM32F411xx) */ +#endif /* defined(STM32F401xx) */ /** @} */ #endif /* STM32_REGISTRY_H */ -- cgit v1.2.3