From 17d265e3bac954e0e934bc528afa8de1ba1f1b60 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 28 Dec 2012 10:41:04 +0000
Subject: Fixed bug 3598720.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4982 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/mac_lld.c | 19 ++++++++++---------
 os/hal/platforms/STM32/mac_lld.h | 20 ++++++++++----------
 2 files changed, 20 insertions(+), 19 deletions(-)

(limited to 'os')

diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
index 0d5590006..36620b934 100644
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@@ -272,7 +272,7 @@ void mac_lld_init(void) {
     ;
 #endif
 
-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
   /* PHY in power down mode until the driver will be started.*/
   mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
 #endif
@@ -306,9 +306,10 @@ void mac_lld_start(MACDriver *macp) {
     ;
 
   /* ISR vector enabled.*/
-  nvicEnableVector(ETH_IRQn, CORTEX_PRIORITY_MASK(STM32_ETH1_IRQ_PRIORITY));
+  nvicEnableVector(ETH_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));
 
-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
   /* PHY in power up mode.*/
   mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
 #endif
@@ -327,7 +328,7 @@ void mac_lld_start(MACDriver *macp) {
   /* Transmitter and receiver enabled.
      Note that the complete setup of the MAC is performed when the link
      status is detected.*/
-#if STM32_IP_CHECKSUM_OFFLOAD
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
   ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
 #else
   ETH->MACCR =                  ETH_MACCR_RE | ETH_MACCR_TE;
@@ -365,7 +366,7 @@ void mac_lld_start(MACDriver *macp) {
 void mac_lld_stop(MACDriver *macp) {
 
   if (macp->state != MAC_STOP) {
-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
     /* PHY in power down mode until the driver will be restarted.*/
     mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
 #endif
@@ -482,7 +483,7 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
 
   /* Unlocks the descriptor and returns it to the DMA engine.*/
   tdp->physdesc->tdes1 = tdp->offset;
-  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_IP_CHECKSUM_OFFLOAD) |
+  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) |
                          STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
                          STM32_TDES0_TCH | STM32_TDES0_OWN;
 
@@ -519,9 +520,9 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
      frames are discarded.*/
   while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
     if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES))
-#if STM32_IP_CHECKSUM_OFFLOAD
-        && !(rdes->rdes0 & STM32_RDES0_FT & (STM32_RDES0_IPHCE |
-                                             STM32_RDES0_PCE))
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
+        && (rdes->rdes0 & STM32_RDES0_FT)
+        && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE))
 #endif
         && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
       /* Found a valid one.*/
diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h
index 9709bcdb7..76241cd52 100644
--- a/os/hal/platforms/STM32/mac_lld.h
+++ b/os/hal/platforms/STM32/mac_lld.h
@@ -124,21 +124,21 @@
  * @brief   Number of available transmit buffers.
  */
 #if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define STM32_MAC_TRANSMIT_BUFFERS  2
+#define STM32_MAC_TRANSMIT_BUFFERS          2
 #endif
 
 /**
  * @brief   Number of available receive buffers.
  */
 #if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define STM32_MAC_RECEIVE_BUFFERS   4
+#define STM32_MAC_RECEIVE_BUFFERS           4
 #endif
 
 /**
  * @brief   Maximum supported frame size.
  */
 #if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define STM32_MAC_BUFFERS_SIZE      1522
+#define STM32_MAC_BUFFERS_SIZE              1522
 #endif
 
 /**
@@ -151,21 +151,21 @@
  *          single search path is performed.
  */
 #if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
-#define STM32_MAC_PHY_TIMEOUT       100
+#define STM32_MAC_PHY_TIMEOUT               100
 #endif
 
 /**
  * @brief   Change the PHY power state inside the driver.
  */
-#if !defined(STM32_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
-#define STM32_ETH1_CHANGE_PHY_STATE TRUE
+#if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
 #endif
 
 /**
  * @brief   ETHD1 interrupt priority level setting.
  */
-#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ETH1_IRQ_PRIORITY     13
+#if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
 #endif
 
 /**
@@ -181,8 +181,8 @@
  *              calculated in hardware.
  *          .
  */
-#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
-#define STM32_IP_CHECKSUM_OFFLOAD   0
+#if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
 #endif
 /** @} */
 
-- 
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