From 0714e7283d1e207bcbcb06cb6fce90ec581bb2d9 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 26 Dec 2017 10:51:37 +0000 Subject: Serial port working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11189 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32H7xx/hal_lld.h | 202 +++++++++++++++------------------ 1 file changed, 90 insertions(+), 112 deletions(-) (limited to 'os') diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 489030d3e..6d7ce589d 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -2280,149 +2280,127 @@ #endif #endif - - - - - - - - - - - - - - - - - - - - - - -#if 0 +#if (STM32_USART16SEL == STM32_USART16SEL_PCLK2) || defined(__DOXYGEN__) /** - * @brief USART1 frequency. + * @brief USART1 clock. */ -#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) #define STM32_USART1CLK STM32_PCLK2 -#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK -#define STM32_USART1CLK STM32_SYSCLK -#elif STM32_USART1SEL == STM32_USART1SEL_HSI + +/** + * @brief USART6 clock. + */ +#define STM32_USART6CLK STM32_PCLK2 +#elif STM32_USART1SEL == STM32_USART16SEL_PLL2_Q_CK +#define STM32_USART1CLK STM32_PLL2_Q_CK +#define STM32_USART6CLK STM32_PLL2_Q_CK +#elif STM32_USART16SEL == STM32_USART16SEL_PLL3_Q_CK +#define STM32_USART1CLK STM32_PLL3_Q_CK +#define STM32_USART6CLK STM32_PLL3_Q_CK +#elif STM32_USART16SEL == STM32_USART16SEL_HSI_KER_CK #define STM32_USART1CLK STM32_HSICLK -#elif STM32_USART1SEL == STM32_USART1SEL_LSE +#define STM32_USART6CLK STM32_HSICLK +#elif STM32_USART16SEL == STM32_USART16SEL_CSI_KER_CK +#define STM32_USART1CLK STM32_CSICLK +#define STM32_USART6CLK STM32_CSICLK +#elif STM32_USART16SEL == STM32_USART16SEL_LSE_CK #define STM32_USART1CLK STM32_LSECLK +#define STM32_USART6CLK STM32_LSECLK #else -#error "invalid source selected for USART1 clock" +#error "invalid source selected for STM32_USART16SEL clock" #endif +#if (STM32_USART234578SEL == STM32_USART234578SEL_PCLK1) || defined(__DOXYGEN__) /** - * @brief USART2 frequency. + * @brief USART2 clock. */ -#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__) #define STM32_USART2CLK STM32_PCLK1 -#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK -#define STM32_USART2CLK STM32_SYSCLK -#elif STM32_USART2SEL == STM32_USART2SEL_HSI -#define STM32_USART2CLK STM32_HSICLK -#elif STM32_USART2SEL == STM32_USART2SEL_LSE -#define STM32_USART2CLK STM32_LSECLK -#else -#error "invalid source selected for USART2 clock" -#endif /** - * @brief USART3 frequency. + * @brief USART3 clock. */ -#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__) #define STM32_USART3CLK STM32_PCLK1 -#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK -#define STM32_USART3CLK STM32_SYSCLK -#elif STM32_USART3SEL == STM32_USART3SEL_HSI -#define STM32_USART3CLK STM32_HSICLK -#elif STM32_USART3SEL == STM32_USART3SEL_LSE -#define STM32_USART3CLK STM32_LSECLK -#else -#error "invalid source selected for USART3 clock" -#endif /** - * @brief UART4 frequency. + * @brief USART4 clock. */ -#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART4CLK STM32_PCLK1 -#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK -#define STM32_UART4CLK STM32_SYSCLK -#elif STM32_UART4SEL == STM32_UART4SEL_HSI -#define STM32_UART4CLK STM32_HSICLK -#elif STM32_UART4SEL == STM32_UART4SEL_LSE -#define STM32_UART4CLK STM32_LSECLK -#else -#error "invalid source selected for UART4 clock" -#endif +#define STM32_USART4CLK STM32_PCLK1 /** - * @brief UART5 frequency. + * @brief USART5 clock. */ -#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART5CLK STM32_PCLK1 -#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK -#define STM32_UART5CLK STM32_SYSCLK -#elif STM32_UART5SEL == STM32_UART5SEL_HSI -#define STM32_UART5CLK STM32_HSICLK -#elif STM32_UART5SEL == STM32_UART5SEL_LSE -#define STM32_UART5CLK STM32_LSECLK -#else -#error "invalid source selected for UART5 clock" -#endif +#define STM32_USART5CLK STM32_PCLK1 /** - * @brief USART6 frequency. + * @brief USART7 clock. */ -#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__) -#define STM32_USART6CLK STM32_PCLK2 -#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK -#define STM32_USART6CLK STM32_SYSCLK -#elif STM32_USART6SEL == STM32_USART6SEL_HSI -#define STM32_USART6CLK STM32_HSICLK -#elif STM32_USART6SEL == STM32_USART6SEL_LSE -#define STM32_USART6CLK STM32_LSECLK -#else -#error "invalid source selected for USART6 clock" -#endif +#define STM32_USART7CLK STM32_PCLK1 /** - * @brief UART7 frequency. + * @brief USART8 clock. */ -#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART7CLK STM32_PCLK1 -#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK -#define STM32_UART7CLK STM32_SYSCLK -#elif STM32_UART7SEL == STM32_UART7SEL_HSI -#define STM32_UART7CLK STM32_HSICLK -#elif STM32_UART7SEL == STM32_UART7SEL_LSE -#define STM32_UART7CLK STM32_LSECLK +#define STM32_USART8CLK STM32_PCLK2 +#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK +#define STM32_USART2CLK STM32_PLL2_Q_CK +#define STM32_USART3CLK STM32_PLL2_Q_CK +#define STM32_USART4CLK STM32_PLL2_Q_CK +#define STM32_USART5CLK STM32_PLL2_Q_CK +#define STM32_USART7CLK STM32_PLL2_Q_CK +#define STM32_USART8CLK STM32_PLL2_Q_CK +#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL3_Q_CK +#define STM32_USART2CLK STM32_PLL3_Q_CK +#define STM32_USART3CLK STM32_PLL3_Q_CK +#define STM32_USART4CLK STM32_PLL3_Q_CK +#define STM32_USART5CLK STM32_PLL3_Q_CK +#define STM32_USART7CLK STM32_PLL3_Q_CK +#define STM32_USART8CLK STM32_PLL3_Q_CK +#elif STM32_USART234578SEL == STM32_USART234578SEL_HSI_KER_CK +#define STM32_USART2CLK STM32_HSICLK +#define STM32_USART3CLK STM32_HSICLK +#define STM32_USART4CLK STM32_HSICLK +#define STM32_USART5CLK STM32_HSICLK +#define STM32_USART7CLK STM32_HSICLK +#define STM32_USART8CLK STM32_HSICLK +#elif STM32_USART234578SEL == STM32_USART234578SEL_CSI_KER_CK +#define STM32_USART2CLK STM32_CSICLK +#define STM32_USART3CLK STM32_CSICLK +#define STM32_USART4CLK STM32_CSICLK +#define STM32_USART5CLK STM32_CSICLK +#define STM32_USART7CLK STM32_CSICLK +#define STM32_USART8CLK STM32_CSICLK +#elif STM32_USART234578SEL == STM32_USART234578SEL_LSE_CK +#define STM32_USART2CLK STM32_LSECLK +#define STM32_USART3CLK STM32_LSECLK +#define STM32_USART4CLK STM32_LSECLK +#define STM32_USART6CLK STM32_LSECLK +#define STM32_USART7CLK STM32_LSECLK +#define STM32_USART8CLK STM32_LSECLK #else -#error "invalid source selected for UART7 clock" +#error "invalid source selected for STM32_USART234578SEL clock" #endif -/** - * @brief UART8 frequency. - */ -#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_UART8CLK STM32_PCLK1 -#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK -#define STM32_UART8CLK STM32_SYSCLK -#elif STM32_UART8SEL == STM32_UART8SEL_HSI -#define STM32_UART8CLK STM32_HSICLK -#elif STM32_UART8SEL == STM32_UART8SEL_LSE -#define STM32_UART8CLK STM32_LSECLK -#else -#error "invalid source selected for UART8 clock" -#endif + + + + + + + + + + + + + + + + + + + + + +#if 0 /** * @brief I2C1 frequency. */ -- cgit v1.2.3