From 06246dd30bb460f7b1eabac7cd9fea16b26c6681 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 25 Jul 2018 18:40:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12196 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/hal/boards/ST_NUCLEO144_L4R5ZI/board.c | 41 ++- os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h | 294 ++++++++++++++++++++++ os/hal/boards/ST_NUCLEO144_L4R5ZI/cfg/board.chcfg | 2 +- os/hal/ports/STM32/STM32L4xx+/hal_lld.h | 46 +--- 4 files changed, 336 insertions(+), 47 deletions(-) (limited to 'os') diff --git a/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.c b/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.c index 5ee0873d7..177ec13c8 100644 --- a/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.c +++ b/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.c @@ -45,6 +45,8 @@ typedef struct { uint32_t odr; uint32_t afrl; uint32_t afrh; + uint32_t ascr; + uint32_t lockr; } gpio_setup_t; /** @@ -92,47 +94,58 @@ typedef struct { static const gpio_config_t gpio_default_config = { #if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, - VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR, + VAL_GPIOA_LOCKR}, #endif #if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, - VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR, + VAL_GPIOB_LOCKR}, #endif #if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, - VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR, + VAL_GPIOC_LOCKR}, #endif #if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, - VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR, + VAL_GPIOD_LOCKR}, #endif #if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, - VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR, + VAL_GPIOE_LOCKR}, #endif #if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, - VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR, + VAL_GPIOF_LOCKR}, #endif #if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, - VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR, + VAL_GPIOG_LOCKR}, #endif #if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, - VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR, + VAL_GPIOH_LOCKR}, #endif #if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR, + VAL_GPIOI_LOCKR}, #endif #if STM32_HAS_GPIOJ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, - VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR, + VAL_GPIOJ_LOCKR}, #endif #if STM32_HAS_GPIOK {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, - VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR, + VAL_GPIOK_LOCKR} #endif }; @@ -143,20 +156,22 @@ static const gpio_config_t gpio_default_config = { static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { gpiop->OTYPER = config->otyper; + gpiop->ASCR = config->ascr; gpiop->OSPEEDR = config->ospeedr; gpiop->PUPDR = config->pupdr; gpiop->ODR = config->odr; gpiop->AFRL = config->afrl; gpiop->AFRH = config->afrh; gpiop->MODER = config->moder; + gpiop->LOCKR = config->lockr; } static void stm32_gpio_init(void) { /* Enabling GPIO-related clocks, the mask comes from the registry header file.*/ - rccResetAHB1(STM32_GPIO_EN_MASK); - rccEnableAHB1(STM32_GPIO_EN_MASK, true); + rccResetAHB2(STM32_GPIO_EN_MASK); + rccEnableAHB2(STM32_GPIO_EN_MASK, true); /* Initializing all the defined GPIO ports.*/ #if STM32_HAS_GPIOA diff --git a/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h b/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h index 70f1a3651..413749955 100644 --- a/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h +++ b/os/hal/boards/ST_NUCLEO144_L4R5ZI/board.h @@ -44,6 +44,8 @@ #define STM32_LSECLK 0U #endif +#define STM32_LSEDRV (3U << 3U) + #if !defined(STM32_HSECLK) #define STM32_HSECLK 8000000U #endif @@ -505,6 +507,10 @@ #define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) #define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) #define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_ASCR_DISABLED(n) (0U << (n)) +#define PIN_ASCR_ENABLED(n) (1U << (n)) +#define PIN_LOCKR_DISABLED(n) (0U << (n)) +#define PIN_LOCKR_ENABLED(n) (1U << (n)) /* * GPIOA setup: @@ -622,6 +628,38 @@ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ PIN_AFIO_AF(GPIOA_ZIO_D20, 6U)) +#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ZIO_D32) | \ + PIN_ASCR_DISABLED(GPIOA_PIN1) | \ + PIN_ASCR_DISABLED(GPIOA_PIN2) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \ + PIN_ASCR_DISABLED(GPIOA_ZIO_D24) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D13) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D12) | \ + PIN_ASCR_DISABLED(GPIOA_ARD_D11) | \ + PIN_ASCR_DISABLED(GPIOA_USB_SOF) | \ + PIN_ASCR_DISABLED(GPIOA_USB_VBUS) | \ + PIN_ASCR_DISABLED(GPIOA_USB_ID) | \ + PIN_ASCR_DISABLED(GPIOA_USB_DM) | \ + PIN_ASCR_DISABLED(GPIOA_USB_DP) | \ + PIN_ASCR_DISABLED(GPIOA_SWDIO) | \ + PIN_ASCR_DISABLED(GPIOA_SWCLK) | \ + PIN_ASCR_DISABLED(GPIOA_ZIO_D20)) +#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_ZIO_D32) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOA_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_A0) | \ + PIN_LOCKR_DISABLED(GPIOA_ZIO_D24) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D13) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D12) | \ + PIN_LOCKR_DISABLED(GPIOA_ARD_D11) | \ + PIN_LOCKR_DISABLED(GPIOA_USB_SOF) | \ + PIN_LOCKR_DISABLED(GPIOA_USB_VBUS) | \ + PIN_LOCKR_DISABLED(GPIOA_USB_ID) | \ + PIN_LOCKR_DISABLED(GPIOA_USB_DM) | \ + PIN_LOCKR_DISABLED(GPIOA_USB_DP) | \ + PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \ + PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \ + PIN_LOCKR_DISABLED(GPIOA_ZIO_D20)) /* * GPIOB setup: @@ -739,6 +777,38 @@ PIN_AFIO_AF(GPIOB_ZIO_D18, 0U) | \ PIN_AFIO_AF(GPIOB_LED3, 0U) | \ PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) +#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ZIO_D33) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_A6) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D27) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D23) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D25) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D22) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D26) | \ + PIN_ASCR_DISABLED(GPIOB_LED2) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D15) | \ + PIN_ASCR_DISABLED(GPIOB_ARD_D14) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D36) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D35) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D19) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D18) | \ + PIN_ASCR_DISABLED(GPIOB_LED3) | \ + PIN_ASCR_DISABLED(GPIOB_ZIO_D17)) +#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_ZIO_D33) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_A6) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D27) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D23) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D25) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D22) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D26) | \ + PIN_LOCKR_DISABLED(GPIOB_LED2) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D15) | \ + PIN_LOCKR_DISABLED(GPIOB_ARD_D14) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D36) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D35) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D19) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D18) | \ + PIN_LOCKR_DISABLED(GPIOB_LED3) | \ + PIN_LOCKR_DISABLED(GPIOB_ZIO_D17)) /* * GPIOC setup: @@ -856,6 +926,38 @@ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) +#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_ARD_A1) | \ + PIN_ASCR_DISABLED(GPIOC_PIN1) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_A7) | \ + PIN_ASCR_DISABLED(GPIOC_ARD_A2) | \ + PIN_ASCR_DISABLED(GPIOC_PIN4) | \ + PIN_ASCR_DISABLED(GPIOC_PIN5) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D16) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D21) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D43) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D44) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D45) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D46) | \ + PIN_ASCR_DISABLED(GPIOC_ZIO_D47) | \ + PIN_ASCR_DISABLED(GPIOC_BUTTON) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_ASCR_DISABLED(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_ARD_A1) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_A7) | \ + PIN_LOCKR_DISABLED(GPIOC_ARD_A2) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOC_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D16) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D21) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D43) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D44) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D45) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D46) | \ + PIN_LOCKR_DISABLED(GPIOC_ZIO_D47) | \ + PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_IN) | \ + PIN_LOCKR_DISABLED(GPIOC_OSC32_OUT)) /* * GPIOD setup: @@ -973,6 +1075,38 @@ PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) +#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_ZIO_D67) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D66) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D48) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D55) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D54) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D53) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D52) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D51) | \ + PIN_ASCR_DISABLED(GPIOD_USART3_RX) | \ + PIN_ASCR_DISABLED(GPIOD_USART3_TX) | \ + PIN_ASCR_DISABLED(GPIOD_PIN10) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D30) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D29) | \ + PIN_ASCR_DISABLED(GPIOD_ZIO_D28) | \ + PIN_ASCR_DISABLED(GPIOD_ARD_D10) | \ + PIN_ASCR_DISABLED(GPIOD_ARD_D9)) +#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_ZIO_D67) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D66) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D48) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D55) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D54) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D53) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D52) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D51) | \ + PIN_LOCKR_DISABLED(GPIOD_USART3_RX) | \ + PIN_LOCKR_DISABLED(GPIOD_USART3_TX) | \ + PIN_LOCKR_DISABLED(GPIOD_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D30) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D29) | \ + PIN_LOCKR_DISABLED(GPIOD_ZIO_D28) | \ + PIN_LOCKR_DISABLED(GPIOD_ARD_D10) | \ + PIN_LOCKR_DISABLED(GPIOD_ARD_D9)) /* * GPIOE setup: @@ -1090,6 +1224,38 @@ PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) +#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_ZIO_D34) | \ + PIN_ASCR_DISABLED(GPIOE_PIN1) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D31) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D60) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D57) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D58) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D59) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D41) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D42) | \ + PIN_ASCR_DISABLED(GPIOE_ARD_D6) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D40) | \ + PIN_ASCR_DISABLED(GPIOE_ARD_D5) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D39) | \ + PIN_ASCR_DISABLED(GPIOE_ARD_D3) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D38) | \ + PIN_ASCR_DISABLED(GPIOE_ZIO_D37)) +#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_ZIO_D34) | \ + PIN_LOCKR_DISABLED(GPIOE_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D31) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D60) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D57) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D58) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D59) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D41) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D42) | \ + PIN_LOCKR_DISABLED(GPIOE_ARD_D6) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D40) | \ + PIN_LOCKR_DISABLED(GPIOE_ARD_D5) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D39) | \ + PIN_LOCKR_DISABLED(GPIOE_ARD_D3) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D38) | \ + PIN_LOCKR_DISABLED(GPIOE_ZIO_D37)) /* * GPIOF setup: @@ -1207,6 +1373,38 @@ PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) +#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_ZIO_D68) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_D69) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_D70) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_A3) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_A8) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_A4) | \ + PIN_ASCR_DISABLED(GPIOF_PIN6) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_D62) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_D61) | \ + PIN_ASCR_DISABLED(GPIOF_ZIO_D63) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_A5) | \ + PIN_ASCR_DISABLED(GPIOF_PIN11) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_D8) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_D7) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_D4) | \ + PIN_ASCR_DISABLED(GPIOF_ARD_D2)) +#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_ZIO_D68) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_D69) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_D70) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_A3) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_A8) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_A4) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_D62) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_D61) | \ + PIN_LOCKR_DISABLED(GPIOF_ZIO_D63) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_A5) | \ + PIN_LOCKR_DISABLED(GPIOF_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_D8) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_D7) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_D4) | \ + PIN_LOCKR_DISABLED(GPIOF_ARD_D2)) /* * GPIOG setup: @@ -1324,6 +1522,38 @@ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \ PIN_AFIO_AF(GPIOG_PIN15, 0U)) +#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_ZIO_D65) | \ + PIN_ASCR_DISABLED(GPIOG_ZIO_D64) | \ + PIN_ASCR_DISABLED(GPIOG_ZIO_D49) | \ + PIN_ASCR_DISABLED(GPIOG_ZIO_D50) | \ + PIN_ASCR_DISABLED(GPIOG_PIN4) | \ + PIN_ASCR_DISABLED(GPIOG_PIN5) | \ + PIN_ASCR_DISABLED(GPIOG_USB_GPIO_OUT) |\ + PIN_ASCR_DISABLED(GPIOG_USB_GPIO_IN) | \ + PIN_ASCR_DISABLED(GPIOG_PIN8) | \ + PIN_ASCR_DISABLED(GPIOG_ARD_D0) | \ + PIN_ASCR_DISABLED(GPIOG_PIN10) | \ + PIN_ASCR_DISABLED(GPIOG_PIN11) | \ + PIN_ASCR_DISABLED(GPIOG_PIN12) | \ + PIN_ASCR_DISABLED(GPIOG_PIN13) | \ + PIN_ASCR_DISABLED(GPIOG_ARD_D1) | \ + PIN_ASCR_DISABLED(GPIOG_PIN15)) +#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_ZIO_D65) | \ + PIN_LOCKR_DISABLED(GPIOG_ZIO_D64) | \ + PIN_LOCKR_DISABLED(GPIOG_ZIO_D49) | \ + PIN_LOCKR_DISABLED(GPIOG_ZIO_D50) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOG_USB_GPIO_OUT) |\ + PIN_LOCKR_DISABLED(GPIOG_USB_GPIO_IN) |\ + PIN_LOCKR_DISABLED(GPIOG_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOG_ARD_D0) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOG_ARD_D1) | \ + PIN_LOCKR_DISABLED(GPIOG_PIN15)) /* * GPIOH setup: @@ -1441,6 +1671,38 @@ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ PIN_AFIO_AF(GPIOH_PIN15, 0U)) +#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_OSC_IN) | \ + PIN_ASCR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_ASCR_DISABLED(GPIOH_PIN2) | \ + PIN_ASCR_DISABLED(GPIOH_PIN3) | \ + PIN_ASCR_DISABLED(GPIOH_PIN4) | \ + PIN_ASCR_DISABLED(GPIOH_PIN5) | \ + PIN_ASCR_DISABLED(GPIOH_PIN6) | \ + PIN_ASCR_DISABLED(GPIOH_PIN7) | \ + PIN_ASCR_DISABLED(GPIOH_PIN8) | \ + PIN_ASCR_DISABLED(GPIOH_PIN9) | \ + PIN_ASCR_DISABLED(GPIOH_PIN10) | \ + PIN_ASCR_DISABLED(GPIOH_PIN11) | \ + PIN_ASCR_DISABLED(GPIOH_PIN12) | \ + PIN_ASCR_DISABLED(GPIOH_PIN13) | \ + PIN_ASCR_DISABLED(GPIOH_PIN14) | \ + PIN_ASCR_DISABLED(GPIOH_PIN15)) +#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_OSC_IN) | \ + PIN_LOCKR_DISABLED(GPIOH_OSC_OUT) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOH_PIN15)) /* * GPIOI setup: @@ -1558,6 +1820,38 @@ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ PIN_AFIO_AF(GPIOI_PIN15, 0U)) +#define VAL_GPIOI_ASCR (PIN_ASCR_DISABLED(GPIOI_PIN0) | \ + PIN_ASCR_DISABLED(GPIOI_PIN1) | \ + PIN_ASCR_DISABLED(GPIOI_PIN2) | \ + PIN_ASCR_DISABLED(GPIOI_PIN3) | \ + PIN_ASCR_DISABLED(GPIOI_PIN4) | \ + PIN_ASCR_DISABLED(GPIOI_PIN5) | \ + PIN_ASCR_DISABLED(GPIOI_PIN6) | \ + PIN_ASCR_DISABLED(GPIOI_PIN7) | \ + PIN_ASCR_DISABLED(GPIOI_PIN8) | \ + PIN_ASCR_DISABLED(GPIOI_PIN9) | \ + PIN_ASCR_DISABLED(GPIOI_PIN10) | \ + PIN_ASCR_DISABLED(GPIOI_PIN11) | \ + PIN_ASCR_DISABLED(GPIOI_PIN12) | \ + PIN_ASCR_DISABLED(GPIOI_PIN13) | \ + PIN_ASCR_DISABLED(GPIOI_PIN14) | \ + PIN_ASCR_DISABLED(GPIOI_PIN15)) +#define VAL_GPIOI_LOCKR (PIN_LOCKR_DISABLED(GPIOI_PIN0) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN1) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN2) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN3) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN4) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN5) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN6) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN7) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN8) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN9) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN10) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN11) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN12) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN13) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN14) | \ + PIN_LOCKR_DISABLED(GPIOI_PIN15)) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/boards/ST_NUCLEO144_L4R5ZI/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO144_L4R5ZI/cfg/board.chcfg index c0d47b881..9f1812467 100644 --- a/os/hal/boards/ST_NUCLEO144_L4R5ZI/cfg/board.chcfg +++ b/os/hal/boards/ST_NUCLEO144_L4R5ZI/cfg/board.chcfg @@ -4,7 +4,7 @@ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32l4xx_board.xsd"> - resources/gencfg/processors/boards/stm32f4xx/templates + resources/gencfg/processors/boards/stm32l4xx/templates .. 5.0.x diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h index 4fad8dbc9..8032c161b 100644 --- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h @@ -286,17 +286,17 @@ #define STM32_ADFSDMSEL_MSI (2 << 3) /**< ADFSDMSEL source is MSI. */ #define STM32_SAI1SEL_MASK (7 << 5) /**< SAI1SEL mask. */ -#define STM32_SAI1SEL_PLLSAI1CLK (0 << 5) /**< SAI1 source is PLLSAI1CLK. */ -#define STM32_SAI1SEL_PLLSAI2CLK (1 << 5) /**< SAI1 source is PLLSAI2CLK. */ -#define STM32_SAI1SEL_PLLSAI3CLK (2 << 5) /**< SAI1 source is PLLSAI3CLK */ +#define STM32_SAI1SEL_PLLSAI1 (0 << 5) /**< SAI1 source is PLLSAI1CLK. */ +#define STM32_SAI1SEL_PLLSAI2 (1 << 5) /**< SAI1 source is PLLSAI2CLK. */ +#define STM32_SAI1SEL_PLL (2 << 5) /**< SAI1 source is PLLSAI3CLK */ #define STM32_SAI1SEL_EXTCLK (3 << 5) /**< SAI1 source is external. */ #define STM32_SAI1SEL_HSI16 (4 << 5) /**< SAI1 source is HSI16. */ #define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ #define STM32_SAI2SEL_MASK (7 << 8) /**< SAI2SEL mask. */ -#define STM32_SAI2SEL_PLLSAI1CLK (0 << 8) /**< SAI2 source is PLLSAI1CLK. */ -#define STM32_SAI2SEL_PLLSAI2CLK (1 << 8) /**< SAI2 source is PLLSAI2CLK. */ -#define STM32_SAI2SEL_PLLSAI3CLK (2 << 8) /**< SAI2 source is PLLSAI3CLK */ +#define STM32_SAI2SEL_PLLSAI1 (0 << 8) /**< SAI2 source is PLLSAI1CLK. */ +#define STM32_SAI2SEL_PLLSAI2 (1 << 8) /**< SAI2 source is PLLSAI2CLK. */ +#define STM32_SAI2SEL_PLL (2 << 8) /**< SAI2 source is PLLSAI3CLK */ #define STM32_SAI2SEL_EXTCLK (3 << 8) /**< SAI2 source is external. */ #define STM32_SAI2SEL_HSI16 (4 << 8) /**< SAI2 source is HSI16. */ #define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/ @@ -511,7 +511,7 @@ * the internal 4MHz MSI clock. */ #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLN_VALUE 120 +#define STM32_PLLN_VALUE 60 #endif /** @@ -545,7 +545,7 @@ * the internal 4MHz MSI clock. */ #if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__) -#define STM32_PLLR_VALUE 4 +#define STM32_PLLR_VALUE 2 #endif /** @@ -769,18 +769,11 @@ #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #endif -/** - * @brief SWPMI1SEL value (SWPMI clock source). - */ -#if !defined(STM32_SWPMI1SEL) || defined(__DOXYGEN__) -#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 -#endif - /** * @brief DFSDMSEL value (DFSDM clock source). */ #if !defined(STM32_DFSDMSEL) || defined(__DOXYGEN__) -#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1 +#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2 #endif /** @@ -1125,7 +1118,6 @@ #endif #endif /* !STM32_HSI16_ENABLED */ -#if STM32_CLOCK_HAS_HSI48 #if STM32_HSI48_ENABLED #else /* !STM32_HSI48_ENABLED */ @@ -1137,7 +1129,6 @@ #error "HSI48 not enabled, required by STM32_CLK48SEL" #endif #endif /* !STM32_HSI48_ENABLED */ -#endif /* STM32_CLOCK_HAS_HSI48 */ /* * HSE related checks. @@ -1314,7 +1305,7 @@ /** * @brief STM32_PLLN field. */ -#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \ +#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 127)) || \ defined(__DOXYGEN__) #define STM32_PLLN (STM32_PLLN_VALUE << 8) #else @@ -1620,7 +1611,7 @@ /** * @brief STM32_PLLSAI1N field. */ -#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 86)) || \ +#if ((STM32_PLLSAI1N_VALUE >= 8) && (STM32_PLLSAI1N_VALUE <= 127)) || \ defined(__DOXYGEN__) #define STM32_PLLSAI1N (STM32_PLLSAI1N_VALUE << 8) #else @@ -1778,7 +1769,7 @@ */ #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI2) || \ (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI2) || \ - (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || \ + (STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \ defined(__DOXYGEN__) #if STM32_PLLCLKIN == 0 @@ -1796,7 +1787,7 @@ /** * @brief STM32_PLLSAI2N field. */ -#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 86)) || \ +#if ((STM32_PLLSAI2N_VALUE >= 8) && (STM32_PLLSAI2N_VALUE <= 127)) || \ defined(__DOXYGEN__) #define STM32_PLLSAI2N (STM32_PLLSAI2N_VALUE << 8) #else @@ -2195,17 +2186,6 @@ #error "invalid source selected for ADC clock" #endif -/** - * @brief SWPMI1 clock frequency. - */ -#if (STM32_SWPMI1SEL == STM32_SWPMI1SEL_PCLK1) || defined(__DOXYGEN__) -#define STM32_SWPMI1CLK STM32_PCLK1 -#elif STM32_SWPMI1SEL == STM32_SWPMI1SEL_HSI16 -#define STM32_SWPMI1CLK STM32_HSI16CLK -#else -#error "invalid source selected for SWPMI1 clock" -#endif - /** * @brief DFSDM clock frequency. */ -- cgit v1.2.3