From 1fa828fe7b35e49a77c232b5d95cc6cf7b429e85 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 3 Feb 2014 10:21:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6662 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/rt/ports/ARMCMx/chcore_v6m.h | 11 +- os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s | 4 +- os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s | 4 +- os/rt/ports/ARMCMx/compilers/GCC/chtypes.h | 2 +- os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s | 122 ++++++++++++++++++++++ os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s | 120 +++++++++++++++++++++ os/rt/ports/ARMCMx/compilers/IAR/chtypes.h | 2 +- os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s | 15 ++- os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s | 15 ++- os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h | 2 +- 10 files changed, 284 insertions(+), 13 deletions(-) create mode 100644 os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s create mode 100644 os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s (limited to 'os/rt/ports') diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h index 54054b163..e80efc9b9 100644 --- a/os/rt/ports/ARMCMx/chcore_v6m.h +++ b/os/rt/ports/ARMCMx/chcore_v6m.h @@ -205,9 +205,16 @@ struct port_intctx { * @details This macro must be inserted at the start of all IRQ handlers * enabled to invoke system APIs. */ +#if defined(__GNUC__) || defined(__DOXYGEN__) #define PORT_IRQ_PROLOGUE() \ - regarm_t _saved_lr; \ - asm volatile ("mov %0, lr" : "=r" (_saved_lr) : : "memory") + regarm_t _saved_lr = (regarm_t)__builtin_return_address(0) +#elif defined(__ICCARM__) +#define PORT_IRQ_PROLOGUE() \ + regarm_t _saved_lr = (regarm_t)__get_LR() +#elif defined(__CC_ARM) +#define PORT_IRQ_PROLOGUE() \ + regarm_t _saved_lr = (regarm_t)__return_address() +#endif /** * @brief IRQ epilogue code. diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s index bd388a0a5..f745d82e6 100644 --- a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s +++ b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s @@ -19,10 +19,10 @@ */ /** - * @file chcoreasm_v6m.s + * @file compilers/GCC/chcoreasm_v6m.s * @brief ARMv6-M architecture port low level code. * - * @addtogroup ARMCMx_CORE + * @addtogroup ARMCMx_GCC_CORE * @{ */ diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s index 9b125ef7c..36567e0b4 100644 --- a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s +++ b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s @@ -19,10 +19,10 @@ */ /** - * @file chcoreasm_v7m.s + * @file compilers/GCC/chcoreasm_v7m.s * @brief ARMv7-M architecture port low level code. * - * @addtogroup ARMCMx_CORE + * @addtogroup ARMCMx_GCC_CORE * @{ */ diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h index 8acbbfa4e..e6f7b21e1 100644 --- a/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h +++ b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h @@ -22,7 +22,7 @@ * @file ARMCMx/compilers/GCC/chtypes.h * @brief ARM Cortex-Mx port system types. * - * @addtogroup ARMCMx_CORE + * @addtogroup ARMCMx_GCC_CORE * @{ */ diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s new file mode 100644 index 000000000..ccaf31326 --- /dev/null +++ b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v6m.s @@ -0,0 +1,122 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/IAR/chcoreasm_v6m.s + * @brief ARMv6-M architecture port low level code. + * + * @addtogroup ARMCMx_IAR_CORE + * @{ + */ + +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + + MODULE ?chcoreasm_v6m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: + ldr r2, =SCB_ICSR + movs r3, #128 +#if CORTEX_ALTERNATE_SWITCH + lsls r3, r3, #21 + str r3, [r2, #0] + cpsie i +#else + lsls r3, r3, #24 + str r3, [r2, #0] +#endif +waithere: + b waithere + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s new file mode 100644 index 000000000..3939dfe63 --- /dev/null +++ b/os/rt/ports/ARMCMx/compilers/IAR/chcoreasm_v7m.s @@ -0,0 +1,120 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file compilers/IAR/chcoreasm_v7m.s + * @brief ARMv7-M architecture port low level code. + * + * @addtogroup ARMCMx_IAR_CORE + * @{ + */ + +#define _FROM_ASM_ +#include "chconf.h" +#include "chcore.h" + +#if !defined(__DOXYGEN__) + + MODULE ?chcoreasm_v7m + + AAPCS INTERWORK, VFP_COMPATIBLE + PRESERVE8 + +CONTEXT_OFFSET SET 12 +SCB_ICSR SET 0xE000ED04 +ICSR_PENDSVSET SET 0x10000000 + + SECTION .text:CODE:NOROOT(2) + + EXTERN chThdExit + EXTERN chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + EXTERN dbg_check_unlock + EXTERN dbg_check_lock +#endif + + THUMB + +/* + * Performs a context switch between two threads. + */ + PUBLIC _port_switch +_port_switch: + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +#if CORTEX_USE_FPU + vpush {s16-s31} +#endif + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] +#if CORTEX_USE_FPU + vpop {s16-s31} +#endif + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + PUBLIC _port_thread_start +_port_thread_start: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +#if CORTEX_SIMPLIFIED_PRIORITY + cpsie i +#else + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 +#endif + mov r0, r5 + blx r4 + bl chThdExit + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + PUBLIC _port_switch_from_isr + PUBLIC _port_exit_from_isr +_port_switch_from_isr: +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_lock +#endif + bl chSchDoReschedule +#if CH_DBG_SYSTEM_STATE_CHECK + bl dbg_check_unlock +#endif +_port_exit_from_isr: +#if CORTEX_SIMPLIFIED_PRIORITY + mov r3, #LWRD SCB_ICSR + movt r3, #HWRD SCB_ICSR + mov r2, #ICSR_PENDSVSET + str r2, [r3] + cpsie i +.L3: b .L3 +#else + svc #0 +#endif + + END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h b/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h index 7d31f51d5..386d7203b 100644 --- a/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h +++ b/os/rt/ports/ARMCMx/compilers/IAR/chtypes.h @@ -22,7 +22,7 @@ * @file ARMCMx/compilers/IAR/chtypes.h * @brief ARM Cortex-Mx port system types. * - * @addtogroup IAR_ARMCMx_CORE + * @addtogroup ARMCMx_IAR_CORE * @{ */ diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s index 282ac547d..732aa992f 100644 --- a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s +++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v6m.s @@ -18,13 +18,20 @@ along with this program. If not, see . */ -/* - * Imports the Cortex-Mx configuration headers. +/** + * @file compilers/RVCT/chcoreasm_v6m.s + * @brief ARMv6-M architecture port low level code. + * + * @addtogroup ARMCMx_RVCT_CORE + * @{ */ + #define _FROM_ASM_ #include "chconf.h" #include "chcore.h" +#if !defined(__DOXYGEN__) + CONTEXT_OFFSET EQU 12 SCB_ICSR EQU 0xE000ED04 @@ -106,3 +113,7 @@ waithere b waithere ENDP END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s index e9404daba..57e074e10 100644 --- a/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s +++ b/os/rt/ports/ARMCMx/compilers/RVCT/chcoreasm_v7m.s @@ -18,13 +18,20 @@ along with this program. If not, see . */ -/* - * Imports the Cortex-Mx configuration headers. +/** + * @file compilers/RVCT/chcoreasm_v7m.s + * @brief ARMv7-M architecture port low level code. + * + * @addtogroup ARMCMx_RVCT_CORE + * @{ */ + #define _FROM_ASM_ #include "chconf.h" #include "chcore.h" +#if !defined(__DOXYGEN__) + CONTEXT_OFFSET EQU 12 SCB_ICSR EQU 0xE000ED04 ICSR_PENDSVSET EQU 0x10000000 @@ -105,3 +112,7 @@ waithere b waithere ENDP END + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h b/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h index 4d3b71e41..3fe32d065 100644 --- a/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h +++ b/os/rt/ports/ARMCMx/compilers/RVCT/chtypes.h @@ -22,7 +22,7 @@ * @file ARMCMx/compilers/RVCT/chtypes.h * @brief ARM Cortex-Mx port system types. * - * @addtogroup RVCT_ARMCMx_CORE + * @addtogroup ARMCMx_RVCT_CORE * @{ */ -- cgit v1.2.3