From 3368f57424db121a96207e9ee6f5e9f746d34ca6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 3 Sep 2013 09:51:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6251 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/rt/ports/ARMCMx/chcore.h | 8 +++---- os/rt/ports/ARMCMx/chcore_v6m.h | 47 ++++++++++++++------------------------- os/rt/ports/ARMCMx/chcore_v7m.h | 49 +++++++++++++++-------------------------- 3 files changed, 39 insertions(+), 65 deletions(-) (limited to 'os/rt/ports/ARMCMx') diff --git a/os/rt/ports/ARMCMx/chcore.h b/os/rt/ports/ARMCMx/chcore.h index ef6720fb2..c2eb68078 100644 --- a/os/rt/ports/ARMCMx/chcore.h +++ b/os/rt/ports/ARMCMx/chcore.h @@ -40,19 +40,19 @@ /** * @brief Macro defining a generic ARM architecture. */ -#define CH_ARCHITECTURE_ARM +#define PORT_ARCHITECTURE_ARM /** * @brief Compiler name and version. */ #if defined(__GNUC__) || defined(__DOXYGEN__) -#define CH_COMPILER_NAME "GCC " __VERSION__ +#define PORT_COMPILER_NAME "GCC " __VERSION__ #elif defined(__ICCARM__) -#define CH_COMPILER_NAME "IAR" +#define PORT_COMPILER_NAME "IAR" #elif defined(__CC_ARM) -#define CH_COMPILER_NAME "RVCT" +#define PORT_COMPILER_NAME "RVCT" #else #error "unsupported compiler" diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h index f72216f95..b39d019e7 100644 --- a/os/rt/ports/ARMCMx/chcore_v6m.h +++ b/os/rt/ports/ARMCMx/chcore_v6m.h @@ -41,38 +41,38 @@ /** * @brief Macro defining the specific ARM architecture. */ -#define CH_ARCHITECTURE_ARM_v6M +#define PORT_ARCHITECTURE_ARM_v6M /** * @brief Name of the implemented architecture. */ -#define CH_ARCHITECTURE_NAME "ARMv6-M" +#define PORT_ARCHITECTURE_NAME "ARMv6-M" /** * @brief Name of the architecture variant. */ -#define CH_CORE_VARIANT_NAME "Cortex-M0" +#define PORT_CORE_VARIANT_NAME "Cortex-M0" #elif (CORTEX_MODEL == CORTEX_M0PLUS) -#define CH_ARCHITECTURE_ARM_v6M -#define CH_ARCHITECTURE_NAME "ARMv6-M" -#define CH_CORE_VARIANT_NAME "Cortex-M0+" +#define PORT_ARCHITECTURE_ARM_v6M +#define PORT_ARCHITECTURE_NAME "ARMv6-M" +#define PORT_CORE_VARIANT_NAME "Cortex-M0+" #endif /** * @brief Port-specific information string. */ #if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__) -#define CH_PORT_INFO "Preemption through NMI" +#define PORT_INFO "Preemption through NMI" #else -#define CH_PORT_INFO "Preemption through PendSV" +#define PORT_INFO "Preemption through PendSV" #endif /** @} */ /** * @brief This port does not support a realtime counter. */ -#define CH_PORT_SUPPORTS_RT FALSE +#define PORT_SUPPORTS_RT FALSE /** * @brief PendSV priority level. @@ -95,8 +95,8 @@ * a stack frame when compiling without optimizations. You may * reduce this value to zero when compiling with optimizations. */ -#if !defined(CH_PORT_IDLE_THREAD_STACK_SIZE) -#define CH_PORT_IDLE_THREAD_STACK_SIZE 16 +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) +#define PORT_IDLE_THREAD_STACK_SIZE 16 #endif /** @@ -108,8 +108,8 @@ * with compiler optimizations disabled. The value can be reduced * when compiler optimizations are enabled. */ -#if !defined(CH_PORT_INT_REQUIRED_STACK) -#define CH_PORT_INT_REQUIRED_STACK 32 +#if !defined(PORT_INT_REQUIRED_STACK) +#define PORT_INT_REQUIRED_STACK 32 #endif /** @@ -202,7 +202,7 @@ struct context { * @details This code usually setup the context switching frame represented * by an @p port_intctx structure. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ +#define PORT_SETUP_CONTEXT(workspace, wsize, pf, arg) { \ tp->p_ctx.r13 = (struct port_intctx *)((uint8_t *)workspace + \ wsize - \ sizeof(struct port_intctx)); \ @@ -211,25 +211,12 @@ struct context { tp->p_ctx.r13->lr = (regarm_t)(_port_thread_start); \ } -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - /** * @brief Computes the thread working area global size. */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(thread_t) + \ - sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - (n) + (CH_PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] +#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ + sizeof(struct port_extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) /** * @brief IRQ prologue code. diff --git a/os/rt/ports/ARMCMx/chcore_v7m.h b/os/rt/ports/ARMCMx/chcore_v7m.h index d768afaef..04d2c0240 100644 --- a/os/rt/ports/ARMCMx/chcore_v7m.h +++ b/os/rt/ports/ARMCMx/chcore_v7m.h @@ -41,25 +41,25 @@ /** * @brief Macro defining the specific ARM architecture. */ -#define CH_ARCHITECTURE_ARM_v7M +#define PORT_ARCHITECTURE_ARM_v7M /** * @brief Name of the implemented architecture. */ -#define CH_ARCHITECTURE_NAME "ARMv7-M" +#define PORT_ARCHITECTURE_NAME "ARMv7-M" /** * @brief Name of the architecture variant. */ -#define CH_CORE_VARIANT_NAME "Cortex-M3" +#define PORT_CORE_VARIANT_NAME "Cortex-M3" #elif (CORTEX_MODEL == CORTEX_M4) -#define CH_ARCHITECTURE_ARM_v7ME -#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#define PORT_ARCHITECTURE_ARM_v7ME +#define PORT_ARCHITECTURE_NAME "ARMv7-ME" #if CORTEX_USE_FPU -#define CH_CORE_VARIANT_NAME "Cortex-M4F" +#define PORT_CORE_VARIANT_NAME "Cortex-M4F" #else -#define CH_CORE_VARIANT_NAME "Cortex-M4" +#define PORT_CORE_VARIANT_NAME "Cortex-M4" #endif #endif @@ -67,16 +67,16 @@ * @brief Port-specific information string. */ #if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) -#define CH_PORT_INFO "Advanced kernel mode" +#define PORT_INFO "Advanced kernel mode" #else -#define CH_PORT_INFO "Compact kernel mode" +#define PORT_INFO "Compact kernel mode" #endif /** @} */ /** * @brief This port supports a realtime counter. */ -#define CH_PORT_SUPPORTS_RT TRUE +#define PORT_SUPPORTS_RT TRUE /** * @brief Disabled value for BASEPRI register. @@ -96,8 +96,8 @@ * a stack frame when compiling without optimizations. You may * reduce this value to zero when compiling with optimizations. */ -#if !defined(CH_PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define CH_PORT_IDLE_THREAD_STACK_SIZE 16 +#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define PORT_IDLE_THREAD_STACK_SIZE 16 #endif /** @@ -109,8 +109,8 @@ * with compiler optimizations disabled. The value can be reduced * when compiler optimizations are enabled. */ -#if !defined(CH_PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) -#define CH_PORT_INT_REQUIRED_STACK 32 +#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__) +#define PORT_INT_REQUIRED_STACK 32 #endif /** @@ -301,7 +301,7 @@ struct context { * @details This code usually setup the context switching frame represented * by an @p port_intctx structure. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ +#define PORT_SETUP_CONTEXT(workspace, wsize, pf, arg) { \ tp->p_ctx.r13 = (struct port_intctx *)((uint8_t *)workspace + \ wsize - \ sizeof(struct port_intctx)); \ @@ -310,25 +310,12 @@ struct context { tp->p_ctx.r13->lr = (regarm_t)(_port_thread_start); \ } -/** - * @brief Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - /** * @brief Computes the thread working area global size. */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(thread_t) + \ - sizeof(struct port_intctx) + \ - sizeof(struct port_extctx) + \ - (n) + (CH_PORT_INT_REQUIRED_STACK)) - -/** - * @brief Static working area allocation. - * @details This macro is used to allocate a static thread working area - * aligned as both position and size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] +#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \ + sizeof(struct port_extctx) + \ + (n) + (PORT_INT_REQUIRED_STACK)) /** * @brief IRQ prologue code. -- cgit v1.2.3