From 33ecba3fd8ea17494b7154d20e677dd50f57b510 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 1 Jun 2011 17:56:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3005 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ports/RVCT/ARMCMx/chcore.h | 221 +++++++++++++++----------------------- os/ports/RVCT/ARMCMx/chcore_v6m.h | 96 +++++++++-------- os/ports/RVCT/ARMCMx/chcore_v7m.h | 165 ++++++++++++++++++++-------- 3 files changed, 261 insertions(+), 221 deletions(-) (limited to 'os/ports/RVCT') diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h index 767f71923..42b397e93 100644 --- a/os/ports/RVCT/ARMCMx/chcore.h +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -29,16 +29,22 @@ #ifndef _CHCORE_H_ #define _CHCORE_H_ -#include "nvic.h" - /*===========================================================================*/ -/* Port constants. */ +/* Port constants (common). */ /*===========================================================================*/ -#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ -#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ -#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ -#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ +/* Added to make the header stand-alone when included from asm.*/ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE (!FALSE) +#endif + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ /* Inclusion of the Cortex-Mx implementation specific parameters.*/ #include "cmparams.h" @@ -51,36 +57,26 @@ #error "unknown or unsupported Cortex-M model" #endif -/*===========================================================================*/ -/* Port statically derived parameters. */ -/*===========================================================================*/ - /** * @brief Total priority levels. */ -#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) /** * @brief Minimum priority level. * @details This minimum priority level is calculated from the number of * priority bits supported by the specific Cortex-Mx implementation. */ -#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) /** * @brief Maximum priority level. * @details The maximum allowed priority level is always zero. */ -#define CORTEX_MAXIMUM_PRIORITY 0 - -/** - * @brief Disabled value for BASEPRI register. - * @note ARMv7-M architecture only. - */ -#define CORTEX_BASEPRI_DISABLED 0 +#define CORTEX_MAXIMUM_PRIORITY 0 /*===========================================================================*/ -/* Port macros. */ +/* Port macros (common). */ /*===========================================================================*/ /** @@ -96,75 +92,56 @@ ((n) << (8 - CORTEX_PRIORITY_BITS)) /*===========================================================================*/ -/* Port configurable parameters. */ +/* Port configurable parameters (common). */ /*===========================================================================*/ /** - * @brief Enables the use of the WFI instruction in the idle thread loop. + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p PORT_INT_REQUIRED_STACK. + * @note In this port it is set to 16 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. */ -#ifndef CORTEX_ENABLE_WFI_IDLE -#define CORTEX_ENABLE_WFI_IDLE FALSE +#ifndef PORT_IDLE_THREAD_STACK_SIZE +#define PORT_IDLE_THREAD_STACK_SIZE 16 #endif /** - * @brief SYSTICK handler priority. - * @note The default SYSTICK handler priority is calculated as the priority - * level in the middle of the numeric priorities range. + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 16 because the function + * @p chSchDoRescheduleI() can have a stack frame, expecially with + * compiler optimizations disabled. */ -#ifndef CORTEX_PRIORITY_SYSTICK -#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) -#else -/* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) -#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" -#endif +#ifndef PORT_INT_REQUIRED_STACK +#define PORT_INT_REQUIRED_STACK 16 #endif /** - * @brief SVCALL handler priority. - * @note The default SVCALL handler priority is calculated as - * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves - * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts - * priority level. - * @note The SVCALL vector is only used in the ARMv7-M port, it is available - * to user in the ARMv6-M port. + * @brief Enables the use of the WFI instruction in the idle thread loop. */ -#ifndef CORTEX_PRIORITY_SVCALL -#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) -#else -/* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) -#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" -#endif +#ifndef CORTEX_ENABLE_WFI_IDLE +#define CORTEX_ENABLE_WFI_IDLE FALSE #endif /** - * @brief PENDSV handler priority. - * @note The default PENDSV handler priority is set at the - * @p CORTEX_MINIMUM_PRIORITY priority level. - * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is - * available to user in the ARMv6-M and ARMv7-M ports. - * @note In the ARMv7-M legacy port this value should be not changed from - * the minimum priority level. + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. */ -#ifndef CORTEX_PRIORITY_PENDSV -#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY +#ifndef CORTEX_PRIORITY_SYSTICK +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) #else /* If it is externally redefined then better perform a validity check on it.*/ -#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV) -#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV" -#endif +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" #endif - -/** - * @brief BASEPRI level within kernel lock. - * @note This value must not mask the SVCALL priority level or the - * kernel would hard fault. - * @note ARMv7-M architecture only. - */ -#ifndef CORTEX_BASEPRI_KERNEL -#define CORTEX_BASEPRI_KERNEL \ - CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) #endif /** @@ -175,11 +152,15 @@ * @note Allowed values are 32 or 64. */ #ifndef CORTEX_STACK_ALIGNMENT -#define CORTEX_STACK_ALIGNMENT 64 +#define CORTEX_STACK_ALIGNMENT 64 #endif /*===========================================================================*/ -/* Port exported info. */ +/* Port derived parameters (common). */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info (common). */ /*===========================================================================*/ /** @@ -187,62 +168,26 @@ */ #define CH_ARCHITECTURE_ARM -#if defined(__DOXYGEN__) -/** - * @brief Macro defining the specific ARM architecture. - * @note This macro is for documentation only, the real name changes - * depending on the selected architecture, the possible names are: - * - CH_ARCHITECTURE_ARM_v6M. - * - CH_ARCHITECTURE_ARM_v7M. - * . - */ -#define CH_ARCHITECTURE_ARM_vxm - /** - * @brief Name of the implemented architecture. - * @note The value is for documentation only, the real value changes - * depending on the selected architecture, the possible values are: - * - "ARMv6-M". - * - "ARMv7-M". - * - "ARMv7-ME". - * . + * @brief Name of the compiler supported by this port. */ -#define CH_ARCHITECTURE_NAME "ARMvx-M" - -/** - * @brief Name of the architecture variant (optional). - * @note The value is for documentation only, the real value changes - * depending on the selected architecture, the possible values are: - * - "Cortex-M0" - * - "Cortex-M1" - * - "Cortex-M3" - * - "Cortex-M4" - * . - */ -#define CH_CORE_VARIANT_NAME "Cortex-Mx" - -#elif CORTEX_MODEL == CORTEX_M4 -#define CH_ARCHITECTURE_ARM_v7M -#define CH_ARCHITECTURE_NAME "ARMv7-ME" -#define CH_CORE_VARIANT_NAME "Cortex-M4" -#elif CORTEX_MODEL == CORTEX_M3 -#define CH_ARCHITECTURE_ARM_v7M -#define CH_ARCHITECTURE_NAME "ARMv7-M" -#define CH_CORE_VARIANT_NAME "Cortex-M3" -#elif CORTEX_MODEL == CORTEX_M1 -#define CH_ARCHITECTURE_ARM_v6M -#define CH_ARCHITECTURE_NAME "ARMv6-M" -#define CH_CORE_VARIANT_NAME "Cortex-M1" -#elif CORTEX_MODEL == CORTEX_M0 -#define CH_ARCHITECTURE_ARM_v6M -#define CH_ARCHITECTURE_NAME "ARMv6-M" -#define CH_CORE_VARIANT_NAME "Cortex-M0" -#endif +#define CH_COMPILER_NAME "RVCT" /*===========================================================================*/ /* Port implementation part (common). */ /*===========================================================================*/ +/* Includes the sub-architecture-specific part.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1) +#include "chcore_v6m.h" +#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) +#include "chcore_v7m.h" +#endif + +#if !defined(_FROM_ASM_) + +#include "nvic.h" + /** * @brief Stack and memory alignment enforcement. */ @@ -259,11 +204,6 @@ typedef uint32_t stkalign_t __attribute__ ((aligned (4))); #error "invalid stack alignment selected" #endif -/** - * @brief Generic ARM register. - */ -typedef void *regarm_t; - #if defined(__DOXYGEN__) /** * @brief Interrupt saved context. @@ -294,6 +234,20 @@ struct context { struct intctx *r13; }; +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (void *)pf; \ + tp->p_ctx.r13->r5 = (void *)arg; \ + tp->p_ctx.r13->lr = (void *)_port_thread_start; \ +} + /** * @brief Enforces a correct alignment for a stack area size value. */ @@ -302,9 +256,9 @@ struct context { /** * @brief Computes the thread working area global size. */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ (n) + (PORT_INT_REQUIRED_STACK)) /** @@ -314,12 +268,7 @@ struct context { */ #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] -/* Includes the architecture-specific implementation part.*/ -#if defined(CH_ARCHITECTURE_ARM_v6M) -#include "chcore_v6m.h" -#elif defined(CH_ARCHITECTURE_ARM_v7M) -#include "chcore_v7m.h" -#endif +#endif /* _FROM_ASM_ */ #endif /* _CHCORE_H_ */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h index 1c4af7da9..bff8c4fe4 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v6m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -29,10 +29,60 @@ #ifndef _CHCORE_V6M_H_ #define _CHCORE_V6M_H_ +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p 0, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV 0 + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v6M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv6-M" + +/** + * @brief Name of the architecture variant. + */ +#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__) +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#elif (CORTEX_MODEL == CORTEX_M1) +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#endif + /*===========================================================================*/ /* Port implementation part. */ /*===========================================================================*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + #if !defined(__DOXYGEN__) struct extctx { regarm_t r0; @@ -58,48 +108,6 @@ struct intctx { }; #endif -/** - * @brief Platform dependent part of the @p chThdInit() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (void *)pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = (void *)_port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 8 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#ifndef PORT_IDLE_THREAD_STACK_SIZE -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port it is conservatively set to 16 because the function - * @p chSchDoRescheduleI() can have a stack frame, expecially with - * compiler optimizations disabled. - */ -#ifndef PORT_INT_REQUIRED_STACK -#define PORT_INT_REQUIRED_STACK 16 -#endif - /** * @brief IRQ prologue code. * @details This macro must be inserted at the start of all IRQ handlers @@ -133,6 +141,8 @@ struct intctx { */ #define port_init() { \ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ } @@ -231,6 +241,8 @@ extern "C" { } #endif +#endif /* _FROM_ASM_ */ + #endif /* _CHCORE_V6M_H_ */ /** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index 7f7d8c5be..14b25fd8c 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -29,10 +29,112 @@ #ifndef _CHCORE_V7M_H_ #define _CHCORE_V7M_H_ +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +/** + * @brief Disabled value for BASEPRI register. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Simplified priority handling flag. + * @details Activating this option will make the Kernel work in compact mode. + */ +#ifndef CORTEX_SIMPLIFIED_PRIORITY +#define CORTEX_SIMPLIFIED_PRIORITY FALSE +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is defaulted to + * @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the + * @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + */ +#ifndef CORTEX_PRIORITY_SVCALL +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#else +/* If it is externally redefined then better perform a validity check on it.*/ +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif +#endif + +/*===========================================================================*/ +/* Port derived parameters. */ +/*===========================================================================*/ + +/** + * @brief BASEPRI level within kernel lock. + * @note In compact kernel mode this constant value is enforced to zero. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#else +#define CORTEX_BASEPRI_KERNEL 0 +#endif + +/** + * @brief PendSV priority level. + * @note This priority is enforced to be equal to @p CORTEX_BASEPRI_KERNEL, + * this handler always have the highest priority that cannot preempt + * the kernel. + */ +#define CORTEX_PRIORITY_PENDSV CORTEX_BASEPRI_KERNEL + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + */ +#define CH_ARCHITECTURE_ARM_v7M + +/** + * @brief Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "ARMv7-M" + +/** + * @brief Name of the architecture variant. + */ +#define CH_CORE_VARIANT_NAME "Cortex-M3" + +#elif (CORTEX_MODEL == CORTEX_M4) +#define CH_ARCHITECTURE_ARM_v7ME +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#endif + +/** + * @brief Port-specific information string. + */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) +#define CH_PORT_INFO "Advanced kernel mode" +#else +#define CH_PORT_INFO "Compact kernel mode" +#endif + /*===========================================================================*/ /* Port implementation part. */ /*===========================================================================*/ +#if !defined(_FROM_ASM_) + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + #if !defined(__DOXYGEN__) struct extctx { regarm_t r0; @@ -58,48 +160,6 @@ struct intctx { }; #endif -/** - * @brief Platform dependent part of the @p chThdCreateI() API. - * @details This code usually setup the context switching frame represented - * by an @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = (void *)pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = (void *)_port_thread_start; \ -} - -/** - * @brief Stack size for the system idle thread. - * @details This size depends on the idle thread implementation, usually - * the idle thread should take no more space than those reserved - * by @p PORT_INT_REQUIRED_STACK. - * @note In this port it is set to 16 because the idle thread does have - * a stack frame when compiling without optimizations. You may - * reduce this value to zero when compiling with optimizations. - */ -#ifndef PORT_IDLE_THREAD_STACK_SIZE -#define PORT_IDLE_THREAD_STACK_SIZE 16 -#endif - -/** - * @brief Per-thread stack overhead for interrupts servicing. - * @details This constant is used in the calculation of the correct working - * area size. - * This value can be zero on those architecture where there is a - * separate interrupt stack and the stack space between @p intctx and - * @p extctx is known to be zero. - * @note In this port it is conservatively set to 16 because the function - * @p chSchDoRescheduleI() can have a stack frame, expecially with - * compiler optimizations disabled. - */ -#ifndef PORT_INT_REQUIRED_STACK -#define PORT_INT_REQUIRED_STACK 16 -#endif - /** * @brief IRQ prologue code. * @details This macro must be inserted at the start of all IRQ handlers @@ -135,6 +195,8 @@ struct intctx { SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ + NVICSetSystemHandlerPriority(HANDLER_PENDSV, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ } @@ -145,10 +207,14 @@ struct intctx { * more actions. * @note In this port this it raises the base priority to kernel level. */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) #define port_lock() { \ register uint32_t basepri __asm("basepri"); \ basepri = CORTEX_BASEPRI_KERNEL; \ } +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_lock() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ /** * @brief Kernel-unlock action. @@ -156,10 +222,14 @@ struct intctx { * more actions. * @note In this port this it lowers the base priority to user level. */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) #define port_unlock() { \ register uint32_t basepri __asm("basepri"); \ basepri = CORTEX_BASEPRI_DISABLED; \ } +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_unlock() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ /** * @brief Kernel-lock action from an interrupt handler. @@ -192,21 +262,28 @@ struct intctx { * @note Interrupt sources above kernel level remains enabled. * @note In this port it raises/lowers the base priority to kernel level. */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) #define port_suspend() { \ register uint32_t basepri __asm("basepri"); \ basepri = CORTEX_BASEPRI_KERNEL; \ - __enable_irq(); \ } +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_suspend() __disable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ /** * @brief Enables all the interrupt sources. * @note In this port it lowers the base priority to user level. */ +#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__) #define port_enable() { \ register uint32_t basepri __asm("basepri"); \ basepri = CORTEX_BASEPRI_DISABLED; \ __enable_irq(); \ } +#else /* CORTEX_SIMPLIFIED_PRIORITY */ +#define port_enable() __enable_irq() +#endif /* CORTEX_SIMPLIFIED_PRIORITY */ /** * @brief Enters an architecture-dependent IRQ-waiting mode. @@ -255,6 +332,8 @@ extern "C" { } #endif +#endif /* _FROM_ASM_ */ + #endif /* _CHCORE_V7M_H_ */ /** @} */ -- cgit v1.2.3