From fa64f08fc1ad45d0984828695697f6abde7e8ffd Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 23 Jul 2013 13:51:02 +0000
Subject: git-svn-id:
 svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6024
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F30x/hal_lld.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'os/hal')

diff --git a/os/hal/platforms/STM32F30x/hal_lld.c b/os/hal/platforms/STM32F30x/hal_lld.c
index 64b691ade..fcfbd4d10 100644
--- a/os/hal/platforms/STM32F30x/hal_lld.c
+++ b/os/hal/platforms/STM32F30x/hal_lld.c
@@ -103,12 +103,18 @@ void hal_lld_init(void) {
   rccResetAPB1(0xFFFFFFFF);
   rccResetAPB2(0xFFFFFFFF);
 
+#if CH_CFG_TIMEDELTA == 0
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_CFG_FREQUENCY - 1;
   SysTick->VAL = 0;
   SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
+#else
+  rccEnableAPB1(RCC_APB1ENR_TIM2EN, TRUE);
+  nvicEnableVector(28, CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
+  TIM2->PSC = STM32_TIMCLK2 / CH_CFG_FREQUENCY - 1;
+#endif
 
   /* DWT cycle counter enable.*/
   SCS_DEMCR |= SCS_DEMCR_TRCENA;
-- 
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