From d671671f159cb6ba8c8ded9c9878cc33680bb729 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 1 Sep 2017 08:31:28 +0000 Subject: Callbacks handling added to STM32 GPIOv2, added F3 support to PAL callbacks demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10517 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c | 116 +++++++ os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h | 55 ++- os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c | 459 ------------------------- os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h | 177 ---------- os/hal/ports/STM32/STM32F3xx/hal_lld.c | 4 + os/hal/ports/STM32/STM32F3xx/platform.mk | 5 +- os/hal/ports/STM32/STM32F3xx/stm32_isr.c | 452 ++++++++++++++++++++++++ os/hal/ports/STM32/STM32F3xx/stm32_isr.h | 119 +++++++ 8 files changed, 743 insertions(+), 644 deletions(-) delete mode 100644 os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c delete mode 100644 os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_isr.c (limited to 'os/hal') diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c index 7cd343f51..6a23eff29 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c @@ -50,6 +50,11 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief Event records for the 16 GPIO EXTI channels. + */ +palevent_t _pal_events[16]; + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -207,6 +212,117 @@ void _pal_lld_setgroupmode(ioportid_t port, } } +/** + * @brief Pad event enable. + * @details This function programs an event callback in the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * @param[in] callback event callback function + * @param[in] arg callback argument + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode, + palcallback_t callback, + void *arg) { + + uint32_t padmask, cridx, crmask, portidx; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* Multiple channel setting of the same channel not allowed, first disable + it. This is done because on STM32 the same channel cannot be mapped on + multiple ports.*/ + osalDbgAssert(((EXTI->RTSR & padmask) == 0U) && + ((EXTI->FTSR & padmask) == 0U), "channel already in use"); + + /* Index and mask of the SYSCFG CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; + crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U)); + + /* Port index is obtained assuming that GPIO ports are placed at regular + 0x400 intervalis in memory space. So far this is true for all devices.*/ + portidx = (uint32_t)port >> 10U; + + /* Port selection in SYSCFG.*/ + SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | portidx; + + /* Programming edge registers.*/ + if (mode & PAL_EVENT_MODE_RISING_EDGE) + EXTI->RTSR |= padmask; + else + EXTI->RTSR &= ~padmask; + if (mode & PAL_EVENT_MODE_FALLING_EDGE) + EXTI->FTSR |= padmask; + else + EXTI->FTSR &= ~padmask; + + /* Programming interrupt and event registers.*/ + if (callback != NULL) { + EXTI->IMR |= padmask; + EXTI->EMR &= ~padmask; + } + else { + EXTI->EMR |= padmask; + EXTI->IMR &= ~padmask; + } + + /* Setting up callback and argument for this event.*/ + _pal_set_event(pad, callback, arg); +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + uint32_t padmask, rtsr1, ftsr1; + + rtsr1 = EXTI->RTSR; + ftsr1 = EXTI->FTSR; + + /* Mask of the pad.*/ + padmask = 1U << (uint32_t)pad; + + /* If either RTRS1 or FTSR1 is enabled then the channel is in use.*/ + if (((rtsr1 | ftsr1) & padmask) != 0U) { + uint32_t cridx, croff, crport, portidx; + + /* Index and mask of the SYSCFG CR register to be used.*/ + cridx = (uint32_t)pad >> 2U; + croff = ((uint32_t)pad & 3U) * 4U; + + /* Port index is obtained assuming that GPIO ports are placed at regular + 0x400 intervalis in memory space. So far this is true for all devices.*/ + portidx = (uint32_t)port >> 10U; + + crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU; + + osalDbgAssert(crport == portidx, "channel mapped on different port"); + + /* Disabling channel.*/ + EXTI->IMR &= ~padmask; + EXTI->EMR &= ~padmask; + EXTI->RTSR = rtsr1 & ~padmask; + EXTI->FTSR = ftsr1 & ~padmask; + EXTI->PR = padmask; + + /* Clearing callback and argument for this event.*/ + _pal_clear_event(pad); + } +} + #endif /* HAL_USE_PAL */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h index 80b1a8fbc..ba90ccafd 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.h @@ -86,12 +86,12 @@ * @{ */ /** - * @brief This mode is implemented as input. + * @brief Implemented as input. */ #define PAL_MODE_RESET PAL_STM32_MODE_INPUT /** - * @brief This mode is implemented as input with pull-up. + * @brief Implemented as input with pull-up. */ #define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP @@ -233,7 +233,7 @@ typedef struct { uint16_t clear; } H; } BSRR; - volatile uint32_t LCKR; + volatile uint32_t LOCKR; volatile uint32_t AFRL; volatile uint32_t AFRH; volatile uint32_t BRR; @@ -329,13 +329,23 @@ typedef uint32_t iomode_t; typedef uint32_t ioline_t; /** - * @brief Port Identifier. + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Type of a port Identifier. * @details This type can be a scalar or some kind of pointer, do not make * any assumption about it, use the provided macros when populating * variables of this type. */ typedef stm32_gpio_t * ioportid_t; +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + /*===========================================================================*/ /* I/O Ports Identifiers. */ /* The low level driver wraps the definitions already present in the STM32 */ @@ -539,7 +549,38 @@ typedef stm32_gpio_t * ioportid_t; */ #define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit) +/** + * @brief Pad event enable. + * @details This function programs an event callback in the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * @param[in] callback event callback function + * @param[in] arg callback argument + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode, callback, arg) \ + _pal_lld_enablepadevent(port, pad, mode, callback, arg) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +#if !defined(__DOXYGEN__) extern const PALConfig pal_default_config; +extern palevent_t _pal_events[16]; +#endif #ifdef __cplusplus extern "C" { @@ -548,6 +589,12 @@ extern "C" { void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode); + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode, + palcallback_t callback, + void *arg); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c deleted file mode 100644 index 179b18986..000000000 --- a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/hal_ext_lld_isr.c - * @brief STM32F3xx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "hal_ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(STM32_DISABLE_EXTI0_HANDLER) -/** - * @brief EXTI[0] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector58) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 0); - EXTI->PR = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[0].cb(&EXTD1, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI1_HANDLER) -/** - * @brief EXTI[1] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector5C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 1); - EXTI->PR = pr; - if (pr & (1U << 1)) - EXTD1.config->channels[1].cb(&EXTD1, 1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI2_HANDLER) -/** - * @brief EXTI[2] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector60) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 2); - EXTI->PR = pr; - if (pr & (1U << 2)) - EXTD1.config->channels[2].cb(&EXTD1, 2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI3_HANDLER) -/** - * @brief EXTI[3] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector64) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 3); - EXTI->PR = pr; - if (pr & (1U << 3)) - EXTD1.config->channels[3].cb(&EXTD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI4_HANDLER) -/** - * @brief EXTI[4] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector68) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 4); - EXTI->PR = pr; - if (pr & (1U << 4)) - EXTD1.config->channels[4].cb(&EXTD1, 4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) -/** - * @brief EXTI[5]...EXTI[9] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector9C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | - (1U << 9)); - EXTI->PR = pr; - if (pr & (1U << 5)) - EXTD1.config->channels[5].cb(&EXTD1, 5); - if (pr & (1U << 6)) - EXTD1.config->channels[6].cb(&EXTD1, 6); - if (pr & (1U << 7)) - EXTD1.config->channels[7].cb(&EXTD1, 7); - if (pr & (1U << 8)) - EXTD1.config->channels[8].cb(&EXTD1, 8); - if (pr & (1U << 9)) - EXTD1.config->channels[9].cb(&EXTD1, 9); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) -/** - * @brief EXTI[10]...EXTI[15] interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE0) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | - (1U << 14) | (1U << 15)); - EXTI->PR = pr; - if (pr & (1U << 10)) - EXTD1.config->channels[10].cb(&EXTD1, 10); - if (pr & (1U << 11)) - EXTD1.config->channels[11].cb(&EXTD1, 11); - if (pr & (1U << 12)) - EXTD1.config->channels[12].cb(&EXTD1, 12); - if (pr & (1U << 13)) - EXTD1.config->channels[13].cb(&EXTD1, 13); - if (pr & (1U << 14)) - EXTD1.config->channels[14].cb(&EXTD1, 14); - if (pr & (1U << 15)) - EXTD1.config->channels[15].cb(&EXTD1, 15); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI16_HANDLER) -/** - * @brief EXTI[16] interrupt handler (PVD). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector44) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 16); - EXTI->PR = pr; - if (pr & (1U << 16)) - EXTD1.config->channels[16].cb(&EXTD1, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI17_HANDLER) -/** - * @brief EXTI[17] interrupt handler (RTC Alarm). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE4) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 17); - EXTI->PR = pr; - if (pr & (1U << 17)) - EXTD1.config->channels[17].cb(&EXTD1, 17); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI18_HANDLER) && STM32_HAS_USB -/** - * @brief EXTI[18] interrupt handler (USB Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(VectorE8) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 18); - EXTI->PR = pr; - if (pr & (1U << 18)) - EXTD1.config->channels[18].cb(&EXTD1, 18); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI19_HANDLER) -/** - * @brief EXTI[19] interrupt handler (Tamper TimeStamp). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector48) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 19); - EXTI->PR = pr; - if (pr & (1U << 19)) - EXTD1.config->channels[19].cb(&EXTD1, 19); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI20_HANDLER) -/** - * @brief EXTI[20] interrupt handler (RTC Wakeup). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector4C) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & (1U << 20); - EXTI->PR = pr; - if (pr & (1U << 20)) - EXTD1.config->channels[20].cb(&EXTD1, 20); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) -/** - * @brief EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector140) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29)); - EXTI->PR = pr; - if (pr & (1U << 21)) - EXTD1.config->channels[21].cb(&EXTD1, 21); - if (pr & (1U << 22)) - EXTD1.config->channels[22].cb(&EXTD1, 22); - if (pr & (1U << 29)) - EXTD1.config->channels[29].cb(&EXTD1, 29); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI30_32_HANDLER) -/** - * @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector144) { - uint32_t pr; - - OSAL_IRQ_PROLOGUE(); - - pr = EXTI->PR; - pr &= EXTI->IMR & ((1U << 30) | (1U << 31)); - EXTI->PR = pr; - if (pr & (1U << 30)) - EXTD1.config->channels[30].cb(&EXTD1, 30); - if (pr & (1U << 31)) - EXTD1.config->channels[31].cb(&EXTD1, 31); - - pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0); - EXTI->PR2 = pr; - if (pr & (1U << 0)) - EXTD1.config->channels[32].cb(&EXTD1, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if !defined(STM32_DISABLE_EXTI33_HANDLER) -/** - * @brief EXTI[33] interrupt handler (COMP7). - * - * @isr - */ -OSAL_IRQ_HANDLER(Vector148) { - uint32_t pr2; - - OSAL_IRQ_PROLOGUE(); - - pr2 = EXTI->PR2; - pr2 = EXTI->IMR & (1U << 1); - EXTI->PR2 = pr2; - if (pr2 & (1U << 1)) - EXTD1.config->channels[33].cb(&EXTD1, 33); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable(void) { - - nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); - nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); - nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); - nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); - nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); - nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); - nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); - nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); - nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); -#if STM32_HAS_USB - nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); -#endif - nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); - nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY); - nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY); - nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY); -#if STM32_EXTI_NUM_LINES >= 34 - nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable(void) { - - nvicDisableVector(EXTI0_IRQn); - nvicDisableVector(EXTI1_IRQn); - nvicDisableVector(EXTI2_TSC_IRQn); - nvicDisableVector(EXTI3_IRQn); - nvicDisableVector(EXTI4_IRQn); - nvicDisableVector(EXTI9_5_IRQn); - nvicDisableVector(EXTI15_10_IRQn); - nvicDisableVector(PVD_IRQn); - nvicDisableVector(RTC_Alarm_IRQn); -#if STM32_HAS_USB - nvicDisableVector(USBWakeUp_IRQn); -#endif - nvicDisableVector(TAMP_STAMP_IRQn); - nvicDisableVector(RTC_WKUP_IRQn); - nvicDisableVector(COMP1_2_3_IRQn); - nvicDisableVector(COMP4_5_6_IRQn); -#if STM32_EXTI_NUM_LINES >= 34 - nvicDisableVector(COMP7_IRQn); -#endif -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h b/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h deleted file mode 100644 index 5c2920eb0..000000000 --- a/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM32F3xx/hal_ext_lld_isr.h - * @brief STM32F3xx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_ISR_H -#define HAL_EXT_LLD_ISR_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI5..9 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI10..15 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI16 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI17 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI18 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI19 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI20 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI21,22,29 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI30..32 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6 -#endif - -/** - * @brief EXTI33 interrupt priority level setting. - */ -#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EXT_EXTI33_IRQ_PRIORITY 6 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable(void); - void ext_lld_exti_irq_disable(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_ISR_H */ - -/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c index c61909bd5..06e80c0fd 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c @@ -115,10 +115,14 @@ void hal_lld_init(void) { /* Initializes the backup domain.*/ hal_lld_backup_domain_init(); + /* DMA subsystems initialization.*/ #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + /* IRQ subsystem initialization.*/ + irqInit(); + /* Programmable voltage detector enable.*/ #if STM32_PVD_ENABLE PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 0109b5a5c..679695552 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -1,5 +1,6 @@ # Required platform files. PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/stm32_isr.c \ $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_lld.c # Required include directories. @@ -16,11 +17,7 @@ endif HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c -endif else -PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/hal_ext_lld_isr.c endif # Drivers compatible with the platform. diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.c b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c new file mode 100644 index 000000000..dd363c536 --- /dev/null +++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c @@ -0,0 +1,452 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32L4xx/stm32_isr.h + * @brief STM32L4xx ISR handler code. + * + * @addtogroup SRM32L4xx_ISR + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#if HAL_USE_EXT +#define exti_serve_irq(pr, channel) { \ + \ + if ((pr) & (1U << (channel))) { \ + EXTD1.config->channels[channel].cb(&EXTD1, channel); \ + } \ +} +#elif HAL_USE_PAL +#define exti_serve_irq(pr, channel) { \ + \ + if ((pr) & (1U << (channel))) { \ + _pal_isr_code(channel); \ + } \ +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if HAL_USE_PAL || HAL_USE_EXT || defined(__DOXYGEN__) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + + exti_serve_irq(pr, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + + exti_serve_irq(pr, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + + exti_serve_irq(pr, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + + exti_serve_irq(pr, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + + exti_serve_irq(pr, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + + exti_serve_irq(pr, 5); + exti_serve_irq(pr, 6); + exti_serve_irq(pr, 7); + exti_serve_irq(pr, 8); + exti_serve_irq(pr, 9); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + + exti_serve_irq(pr, 10); + exti_serve_irq(pr, 11); + exti_serve_irq(pr, 12); + exti_serve_irq(pr, 13); + exti_serve_irq(pr, 14); + exti_serve_irq(pr, 15); + + OSAL_IRQ_EPILOGUE(); +} + +#if HAL_USE_EXT || defined(__DOXYGEN__) +#if !defined(STM32_DISABLE_EXTI16_HANDLER) +/** + * @brief EXTI[16] interrupt handler (PVD). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector44) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 16); + EXTI->PR = pr; + if (pr & (1U << 16)) + EXTD1.config->channels[16].cb(&EXTD1, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI17_HANDLER) +/** + * @brief EXTI[17] interrupt handler (RTC Alarm). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE4) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 17); + EXTI->PR = pr; + if (pr & (1U << 17)) + EXTD1.config->channels[17].cb(&EXTD1, 17); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI18_HANDLER) && STM32_HAS_USB +/** + * @brief EXTI[18] interrupt handler (USB Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE8) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 18); + EXTI->PR = pr; + if (pr & (1U << 18)) + EXTD1.config->channels[18].cb(&EXTD1, 18); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI19_HANDLER) +/** + * @brief EXTI[19] interrupt handler (Tamper TimeStamp). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector48) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 19); + EXTI->PR = pr; + if (pr & (1U << 19)) + EXTD1.config->channels[19].cb(&EXTD1, 19); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI20_HANDLER) +/** + * @brief EXTI[20] interrupt handler (RTC Wakeup). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector4C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 20); + EXTI->PR = pr; + if (pr & (1U << 20)) + EXTD1.config->channels[20].cb(&EXTD1, 20); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER) +/** + * @brief EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector140) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 21) | (1U << 22) | (1U << 29)); + EXTI->PR = pr; + if (pr & (1U << 21)) + EXTD1.config->channels[21].cb(&EXTD1, 21); + if (pr & (1U << 22)) + EXTD1.config->channels[22].cb(&EXTD1, 22); + if (pr & (1U << 29)) + EXTD1.config->channels[29].cb(&EXTD1, 29); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI30_32_HANDLER) +/** + * @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector144) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 30) | (1U << 31)); + EXTI->PR = pr; + if (pr & (1U << 30)) + EXTD1.config->channels[30].cb(&EXTD1, 30); + if (pr & (1U << 31)) + EXTD1.config->channels[31].cb(&EXTD1, 31); + + pr = EXTI->PR2 & EXTI->IMR2 & (1U << 0); + EXTI->PR2 = pr; + if (pr & (1U << 0)) + EXTD1.config->channels[32].cb(&EXTD1, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI33_HANDLER) +/** + * @brief EXTI[33] interrupt handler (COMP7). + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector148) { + uint32_t pr2; + + OSAL_IRQ_PROLOGUE(); + + pr2 = EXTI->PR2; + pr2 = EXTI->IMR & (1U << 1); + EXTI->PR2 = pr2; + if (pr2 & (1U << 1)) + EXTD1.config->channels[33].cb(&EXTD1, 33); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#endif /* HAL_USE_EXT */ + +#endif /* HAL_USE_PAL || HAL_USE_EXT */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables IRQ sources. + * + * @notapi + */ +void irqInit(void) { + +#if HAL_USE_PAL || HAL_USE_EXT + nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY); + nvicEnableVector(EXTI2_TSC_IRQn, STM32_IRQ_EXTI2_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY); +#if HAL_USE_EXT + nvicEnableVector(PVD_PVM_IRQn, STM32_IRQ_EXTI1635_38_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_IRQ_EXTI18_PRIORITY); + nvicEnableVector(TAMP_STAMP_IRQn, STM32_IRQ_EXTI19_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_IRQ_EXTI20_PRIORITY); + nvicEnableVector(COMP_IRQn, STM32_IRQ_EXTI21_22_PRIORITY); +#endif +#endif +} + +/** + * @brief Disables IRQ sources. + * + * @notapi + */ +void irqDeinit(void) { + +#if HAL_USE_PAL || HAL_USE_EXT + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_TSC_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); +#if HAL_USE_EXT + nvicEnableVector(PVD_IRQn, STM32_IRQ_EXTI16_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_IRQ_EXTI17_PRIORITY); +#if STM32_HAS_USB + nvicEnableVector(USBWakeUp_IRQn, STM32_IRQ_EXTI18_PRIORITY); +#endif + nvicEnableVector(TAMP_STAMP_IRQn, STM32_IRQ_EXTI19_PRIORITY); + nvicEnableVector(RTC_WKUP_IRQn, STM32_IRQ_EXTI20_PRIORITY); + nvicEnableVector(COMP1_2_3_IRQn, STM32_IRQ_EXTI21_22_29_PRIORITY); + nvicEnableVector(COMP4_5_6_IRQn, STM32_IRQ_EXTI30_32_PRIORITY); +#if STM32_EXTI_NUM_LINES >= 34 + nvicEnableVector(COMP7_IRQn, STM32_IRQ_EXTI33_PRIORITY); +#endif +#endif +#endif +} + +/** @} */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h index a483c2eee..5f56b295d 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h @@ -116,6 +116,116 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI0_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI1_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI2_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI3_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI4_PRIORITY 6 +#endif + +/** + * @brief EXTI5..9 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#endif + +/** + * @brief EXTI10..15 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI16_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI17_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI18_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI19_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI20_PRIORITY 6 +#endif + +/** + * @brief EXTI21,22,29 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI21_22_29_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI21_22_29_PRIORITY 6 +#endif + +/** + * @brief EXTI30..32 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI30_32_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI30_32_PRIORITY 6 +#endif + +/** + * @brief EXTI33 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI33_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI33_PRIORITY 6 +#endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -132,6 +242,15 @@ /* External declarations. */ /*===========================================================================*/ +#ifdef __cplusplus +extern "C" { +#endif + void irqInit(void); + void irqDeinit(void); +#ifdef __cplusplus +} +#endif + #endif /* STM32_ISR_H */ /** @} */ -- cgit v1.2.3