From cced334724aec1f39d683adcda6984543095ba8c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 25 Feb 2013 11:58:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5318 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/mmcsd.h | 26 ++ os/hal/platforms/STM32/icu_lld.h | 2 +- os/hal/platforms/STM32/sdc_lld.h | 26 -- os/hal/src/sdc.c | 4 +- os/hal/templates/adc_lld.c | 6 +- os/hal/templates/can_lld.c | 27 +- os/hal/templates/ext_lld.c | 12 +- os/hal/templates/gpt_lld.c | 12 +- os/hal/templates/hal_lld.c | 151 +---------- os/hal/templates/i2c_lld.c | 18 +- os/hal/templates/icu_lld.c | 39 ++- os/hal/templates/icu_lld.h | 17 ++ os/hal/templates/mac_lld.c | 514 ++++--------------------------------- os/hal/templates/mac_lld.h | 15 +- os/hal/templates/meta/driver_lld.c | 4 +- os/hal/templates/pal_lld.c | 6 + os/hal/templates/sdc_lld.c | 32 ++- 17 files changed, 251 insertions(+), 660 deletions(-) (limited to 'os/hal') diff --git a/os/hal/include/mmcsd.h b/os/hal/include/mmcsd.h index c782ab7a2..5ff3082c7 100644 --- a/os/hal/include/mmcsd.h +++ b/os/hal/include/mmcsd.h @@ -218,6 +218,32 @@ typedef struct { /* Driver macros. */ /*===========================================================================*/ +/** + * @name R1 response utilities + * @{ + */ +/** + * @brief Evaluates to @p TRUE if the R1 response contains error flags. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0) + +/** + * @brief Returns the status field of an R1 response. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15) + +/** + * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. + * + * @param[in] r1 the r1 response + */ +#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) +/** @} */ + /** * @name Macro Functions * @{ diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index 253adee4a..5e387eba9 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -222,7 +222,7 @@ typedef enum { typedef uint32_t icufreq_t; /** - * @brief ICU channel. + * @brief ICU channel type. */ typedef enum { ICU_CHANNEL_1 = 0, /**< Use TIMxCH1. */ diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h index 4ae6a6163..3336e01f5 100644 --- a/os/hal/platforms/STM32/sdc_lld.h +++ b/os/hal/platforms/STM32/sdc_lld.h @@ -271,32 +271,6 @@ struct SDCDriver { /* Driver macros. */ /*===========================================================================*/ -/** - * @name R1 response utilities - * @{ - */ -/** - * @brief Evaluates to @p TRUE if the R1 response contains error flags. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_ERROR(r1) (((r1) & MMCSD_R1_ERROR_MASK) != 0) - -/** - * @brief Returns the status field of an R1 response. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_STS(r1) (((r1) >> 9) & 15) - -/** - * @brief Evaluates to @p TRUE if the R1 response indicates a locked card. - * - * @param[in] r1 the r1 response - */ -#define MMCSD_R1_IS_CARD_LOCKED(r1) (((r1) >> 21) & 1) -/** @} */ - /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/src/sdc.c b/os/hal/src/sdc.c index 30f24af5b..929f58a46 100644 --- a/os/hal/src/sdc.c +++ b/os/hal/src/sdc.c @@ -218,8 +218,8 @@ bool_t sdcConnect(SDCDriver *sdcp) { else { #if SDC_MMC_SUPPORT /* MMC or SD V1.1 detection.*/ - if (sdc_lld_send_cmd_short_crc(sdcp, SDMMC_CMD_APP_CMD, 0, resp) || - SDC_R1_ERROR(resp[0])) + if (sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_APP_CMD, 0, resp) || + MMCSD_R1_ERROR(resp[0])) sdcp->cardmode = SDC_MODE_CARDTYPE_MMC; else #endif /* SDC_MMC_SUPPORT */ diff --git a/os/hal/templates/adc_lld.c b/os/hal/templates/adc_lld.c index 1ea117d8a..8b058ab3c 100644 --- a/os/hal/templates/adc_lld.c +++ b/os/hal/templates/adc_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief ADC1 driver identifier.*/ +/** + * @brief ADC1 driver identifier. + */ #if PLATFORM_ADC_USE_ADC1 || defined(__DOXYGEN__) ADCDriver ADCD1; #endif @@ -124,6 +126,7 @@ void adc_lld_stop(ADCDriver *adcp) { */ void adc_lld_start_conversion(ADCDriver *adcp) { + (void)adcp; } /** @@ -135,6 +138,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { */ void adc_lld_stop_conversion(ADCDriver *adcp) { + (void)adcp; } #endif /* HAL_USE_ADC */ diff --git a/os/hal/templates/can_lld.c b/os/hal/templates/can_lld.c index f9385fe77..b00cc2c8b 100644 --- a/os/hal/templates/can_lld.c +++ b/os/hal/templates/can_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief CAN1 driver identifier.*/ +/** + * @brief CAN1 driver identifier. + */ #if PLATFORM_CAN_USE_CAN1 || defined(__DOXYGEN__) CANDriver CAND1; #endif @@ -129,6 +131,8 @@ void can_lld_stop(CANDriver *canp) { */ bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + (void)canp; + switch (mailbox) { case CAN_ANY_MAILBOX: return FALSE; @@ -156,6 +160,10 @@ void can_lld_transmit(CANDriver *canp, canmbx_t mailbox, const CANTxFrame *ctfp) { + (void)canp; + (void)mailbox; + (void)ctfp; + } /** @@ -172,13 +180,16 @@ void can_lld_transmit(CANDriver *canp, */ bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + (void)canp; + (void)mailbox; + switch (mailbox) { case CAN_ANY_MAILBOX: - return FALSE + return FALSE; case 1: - return FALSE + return FALSE; case 2: - return FALSE + return FALSE; default: return FALSE; } @@ -197,6 +208,10 @@ void can_lld_receive(CANDriver *canp, canmbx_t mailbox, CANRxFrame *crfp) { + (void)canp; + (void)mailbox; + (void)crfp; + } #if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) @@ -209,6 +224,8 @@ void can_lld_receive(CANDriver *canp, */ void can_lld_sleep(CANDriver *canp) { + (void)canp; + } /** @@ -220,6 +237,8 @@ void can_lld_sleep(CANDriver *canp) { */ void can_lld_wakeup(CANDriver *canp) { + (void)canp; + } #endif /* CAN_USE_SLEEP_MODE */ diff --git a/os/hal/templates/ext_lld.c b/os/hal/templates/ext_lld.c index e0d7575fd..e1ce295b7 100644 --- a/os/hal/templates/ext_lld.c +++ b/os/hal/templates/ext_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief EXT1 driver identifier.*/ +/** + * @brief EXT1 driver identifier. + */ #if PLATFORM_EXT_USE_EXT1 || defined(__DOXYGEN__) EXTDriver EXTD1; #endif @@ -103,7 +105,7 @@ void ext_lld_start(EXTDriver *extp) { */ void ext_lld_stop(EXTDriver *extp) { - if (extp->state == EXT_READY) { + if (extp->state == EXT_ACTIVE) { /* Resets the peripheral.*/ /* Disables the peripheral.*/ @@ -125,6 +127,9 @@ void ext_lld_stop(EXTDriver *extp) { */ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { + (void)extp; + (void)channel; + } /** @@ -137,6 +142,9 @@ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { */ void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) { + (void)extp; + (void)channel; + } #endif /* HAL_USE_EXT */ diff --git a/os/hal/templates/gpt_lld.c b/os/hal/templates/gpt_lld.c index 6ba3aea27..be2241144 100644 --- a/os/hal/templates/gpt_lld.c +++ b/os/hal/templates/gpt_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief GPTD1 driver identifier.*/ +/** + * @brief GPTD1 driver identifier. + */ #if PLATFORM_GPT_USE_GPT1 || defined(__DOXYGEN__) GPTDriver GPTD1; #endif @@ -125,6 +127,9 @@ void gpt_lld_stop(GPTDriver *gptp) { */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + (void)gptp; + (void)interval; + } /** @@ -136,6 +141,8 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { */ void gpt_lld_stop_timer(GPTDriver *gptp) { + (void)gptp; + } /** @@ -151,6 +158,9 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + (void)gptp; + (void)interval; + } #endif /* HAL_USE_GPT */ diff --git a/os/hal/templates/hal_lld.c b/os/hal/templates/hal_lld.c index c903069f9..7f826470a 100644 --- a/os/hal/templates/hal_lld.c +++ b/os/hal/templates/hal_lld.c @@ -19,8 +19,8 @@ */ /** - * @file STM32F30x/hal_lld.c - * @brief STM32F30x HAL subsystem low level driver source. + * @file templates/hal_lld.c + * @brief HAL Driver subsystem low level driver source template. * * @addtogroup HAL * @{ @@ -45,49 +45,6 @@ /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Initializes the backup domain. - * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. - */ -static void hal_lld_backup_domain_init(void) { - - /* Backup domain access enabled and left open.*/ - PWR->CR |= PWR_CR_DBP; - - /* Reset BKP domain if different clock source selected.*/ - if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){ - /* Backup domain reset.*/ - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - } - - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED -#if defined(STM32_LSE_BYPASS) - /* LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; -#else - /* No LSE Bypass.*/ - RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON; -#endif - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ -#endif - -#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ - if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { - /* Selects clock source.*/ - RCC->BDCR |= STM32_RTCSEL; - - /* RTC clock enabled.*/ - RCC->BDCR |= RCC_BDCR_RTCEN; - } -#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ -} - /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -103,111 +60,19 @@ static void hal_lld_backup_domain_init(void) { */ void hal_lld_init(void) { - /* Reset of all peripherals.*/ - rccResetAPB1(0xFFFFFFFF); - rccResetAPB2(0xFFFFFFFF); - - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - - /* PWR clock enabled.*/ - rccEnablePWRInterface(FALSE); - - /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); - -#if defined(STM32_DMA_REQUIRED) - dmaInit(); -#endif - - /* Programmable voltage detector enable.*/ -#if STM32_PVD_ENABLE - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ - - /* SYSCFG clock enabled here because it is a multi-functional unit shared - among multiple drivers.*/ - rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); - - /* USB IRQ relocated to not conflict with CAN.*/ - SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP; } /** - * @brief STM32 clocks and PLL initialization. + * @brief Platform early initialization. * @note All the involved constants come from the file @p board.h. - * @note This function should be invoked just after the system reset. + * @note This function is meant to be invoked early during the system + * initialization, it is usually invoked from the file + * @p board.c. * * @special */ -void stm32_clock_init(void) { - -#if !STM32_NO_INIT - /* HSI setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; /* Wait until HSI is stable. */ - RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ - RCC->CFGR = 0; /* CFGR reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Waits until HSI is selected. */ - -#if STM32_HSE_ENABLED - /* HSE activation.*/ -#if defined(STM32_HSE_BYPASS) - /* HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; -#else - /* No HSE Bypass.*/ - RCC->CR |= RCC_CR_HSEON; -#endif - while (!(RCC->CR & RCC_CR_HSERDY)) - ; /* Waits until HSE is stable. */ -#endif - -#if STM32_LSI_ENABLED - /* LSI activation.*/ - RCC->CSR |= RCC_CSR_LSION; - while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) - ; /* Waits until LSI is stable. */ -#endif - - /* Clock settings.*/ - RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | - STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 | - STM32_HPRE; - RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV; - RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW | - STM32_USART2SW | STM32_TIM8SW | STM32_TIM1SW | - STM32_I2C2SW | STM32_I2C1SW | STM32_USART1SW; - -#if STM32_ACTIVATE_PLL - /* PLL activation.*/ - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; /* Waits until PLL is stable. */ -#endif - - /* Flash setup and final clock selection. */ - FLASH->ACR = STM32_FLASHBITS; - - /* Switching to the configured clock source if it is different from HSI.*/ -#if (STM32_SW != STM32_SW_HSI) - /* Switches clock source.*/ - RCC->CFGR |= STM32_SW; - while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) - ; /* Waits selection complete. */ -#endif -#endif /* !STM32_NO_INIT */ +void platform_early_init(void) { + } /** @} */ diff --git a/os/hal/templates/i2c_lld.c b/os/hal/templates/i2c_lld.c index e4a08f848..9c47cd40e 100644 --- a/os/hal/templates/i2c_lld.c +++ b/os/hal/templates/i2c_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief I2C1 driver identifier.*/ +/** + * @brief I2C1 driver identifier. + */ #if PLATFORM_I2C_USE_I2C1 || defined(__DOXYGEN__) I2CDriver I2CD1; #endif @@ -141,6 +143,12 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { + (void)i2cp; + (void)addr; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + return RDY_OK; } @@ -174,6 +182,14 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { + (void)i2cp; + (void)addr; + (void)txbuf; + (void)txbytes; + (void)rxbuf; + (void)rxbytes; + (void)timeout; + return RDY_OK; } diff --git a/os/hal/templates/icu_lld.c b/os/hal/templates/icu_lld.c index 0e24b8a57..008d75c22 100644 --- a/os/hal/templates/icu_lld.c +++ b/os/hal/templates/icu_lld.c @@ -39,6 +39,13 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief ICU1 driver identifier. + */ +#if PLATFORM_ICU_USE_ICU1 || defined(__DOXYGEN__) +ICUDriver ICUD1; +#endif + /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ @@ -62,6 +69,10 @@ */ void icu_lld_init(void) { +#if PLATFORM_ICU_USE_ICU1 + /* Driver initialization.*/ + icuObjectInit(&ICUD1); +#endif /* PLATFORM_ICU_USE_ICU1 */ } /** @@ -74,9 +85,15 @@ void icu_lld_init(void) { void icu_lld_start(ICUDriver *icup) { if (icup->state == ICU_STOP) { - /* Clock activation.*/ + /* Enables the pehipheral.*/ +#if PLATFORM_ICU_USE_ICU1 + if (&ICUD1 == icup) { + + } +#endif /* PLATFORM_ICU_USE_ICU1 */ } - /* Configuration.*/ + /* Configures the peripheral.*/ + } /** @@ -89,8 +106,14 @@ void icu_lld_start(ICUDriver *icup) { void icu_lld_stop(ICUDriver *icup) { if (icup->state == ICU_READY) { - /* Clock deactivation.*/ + /* Resets the peripheral.*/ + /* Disables the peripheral.*/ +#if PLATFORM_ICU_USE_ICU1 + if (&ICUD1 == icup) { + + } +#endif /* PLATFORM_ICU_USE_ICU1 */ } } @@ -103,6 +126,8 @@ void icu_lld_stop(ICUDriver *icup) { */ void icu_lld_enable(ICUDriver *icup) { + (void)icup; + } /** @@ -114,6 +139,8 @@ void icu_lld_enable(ICUDriver *icup) { */ void icu_lld_disable(ICUDriver *icup) { + (void)icup; + } /** @@ -128,6 +155,9 @@ void icu_lld_disable(ICUDriver *icup) { */ icucnt_t icu_lld_get_width(ICUDriver *icup) { + (void)icup; + + return 0; } /** @@ -142,6 +172,9 @@ icucnt_t icu_lld_get_width(ICUDriver *icup) { */ icucnt_t icu_lld_get_period(ICUDriver *icup) { + (void)icup; + + return 0; } #endif /* HAL_USE_ICU */ diff --git a/os/hal/templates/icu_lld.h b/os/hal/templates/icu_lld.h index c245ed58c..b30733a43 100644 --- a/os/hal/templates/icu_lld.h +++ b/os/hal/templates/icu_lld.h @@ -43,6 +43,19 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ +/** + * @brief ICU driver enable switch. + * @details If set to @p TRUE the support for ICU1 is included. + */ +#if !defined(PLATFORM_ICU_USE_ICU1) || defined(__DOXYGEN__) +#define PLATFORM_ICU_USE_ICU1 FALSE +#endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -125,6 +138,10 @@ struct ICUDriver { /* External declarations. */ /*===========================================================================*/ +#if PLATFORM_ICU_USE_ICU1 && !defined(__DOXYGEN__) +extern ICUDriver ICUD1; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/templates/mac_lld.c b/os/hal/templates/mac_lld.c index d115a750b..b442d0879 100644 --- a/os/hal/templates/mac_lld.c +++ b/os/hal/templates/mac_lld.c @@ -19,8 +19,8 @@ */ /** - * @file STM32/mac_lld.c - * @brief STM32 low level MAC driver code. + * @file templates/mac_lld.c + * @brief MAC Driver subsystem low level driver source template. * * @addtogroup MAC * @{ @@ -38,169 +38,29 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define BUFFER_SIZE ((((STM32_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) - -/* MII divider optimal value.*/ -#if (STM32_HCLK >= 150000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div102 -#elif (STM32_HCLK >= 100000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div62 -#elif (STM32_HCLK >= 60000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div42 -#elif (STM32_HCLK >= 35000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div26 -#elif (STM32_HCLK >= 20000000) -#define MACMIIDR_CR ETH_MACMIIAR_CR_Div16 -#else -#error "STM32_HCLK below minimum frequency for ETH operations (20MHz)" -#endif - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ /** - * @brief Ethernet driver 1. + * @brief MAC1 driver identifier. */ +#if PLATFORM_MAC_USE_MAC1 || defined(__DOXYGEN__) MACDriver ETHD1; +#endif /*===========================================================================*/ /* Driver local variables. */ /*===========================================================================*/ -static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, - 0x37, 0x01, 0x10}; - -static stm32_eth_rx_descriptor_t rd[STM32_MAC_RECEIVE_BUFFERS]; -static stm32_eth_tx_descriptor_t td[STM32_MAC_TRANSMIT_BUFFERS]; - -static uint32_t rb[STM32_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; -static uint32_t tb[STM32_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; - /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Writes a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - */ -static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - - ETH->MACMIIDR = value; - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | - ETH_MACMIIAR_MW | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; -} - -/** - * @brief Reads a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The PHY register content. - */ -static uint32_t mii_read(MACDriver *macp, uint32_t reg) { - - ETH->MACMIIAR = macp->phyaddr | (reg << 6) | MACMIIDR_CR | ETH_MACMIIAR_MB; - while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0) - ; - return ETH->MACMIIDR; -} - -#if !defined(BOARD_PHY_ADDRESS) -/** - * @brief PHY address detection. - * - * @param[in] macp pointer to the @p MACDriver object - */ -static void mii_find_phy(MACDriver *macp) { - uint32_t i; - -#if STM32_MAC_PHY_TIMEOUT > 0 - halrtcnt_t start = halGetCounterValue(); - halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT); - while (halIsCounterWithin(start, timeout)) { -#endif - for (i = 0; i < 31; i++) { - macp->phyaddr = i << 11; - ETH->MACMIIDR = (i << 6) | MACMIIDR_CR; - if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) && - ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { - return; - } - } -#if STM32_MAC_PHY_TIMEOUT > 0 - } -#endif - /* Wrong or defective board.*/ - chSysHalt(); -} -#endif - -/** - * @brief MAC address setup. - * - * @param[in] p pointer to a six bytes buffer containing the MAC - * address - */ -static void mac_lld_set_address(const uint8_t *p) { - - /* MAC address configuration, only a single address comparator is used, - hash table not used.*/ - ETH->MACA0HR = ((uint32_t)p[5] << 8) | - ((uint32_t)p[4] << 0); - ETH->MACA0LR = ((uint32_t)p[3] << 24) | - ((uint32_t)p[2] << 16) | - ((uint32_t)p[1] << 8) | - ((uint32_t)p[0] << 0); - ETH->MACA1HR = 0x0000FFFF; - ETH->MACA1LR = 0xFFFFFFFF; - ETH->MACA2HR = 0x0000FFFF; - ETH->MACA2LR = 0xFFFFFFFF; - ETH->MACA3HR = 0x0000FFFF; - ETH->MACA3LR = 0xFFFFFFFF; - ETH->MACHTHR = 0; - ETH->MACHTLR = 0; -} - /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ -CH_IRQ_HANDLER(ETH_IRQHandler) { - uint32_t dmasr; - - CH_IRQ_PROLOGUE(); - - dmasr = ETH->DMASR; - ETH->DMASR = dmasr; /* Clear status bits.*/ - - if (dmasr & ETH_DMASR_RS) { - /* Data Received.*/ - chSysLockFromIsr(); - chSemResetI(ÐD1.rdsem, 0); -#if MAC_USE_EVENTS - chEvtBroadcastI(ÐD1.rdevent); -#endif - chSysUnlockFromIsr(); - } - - if (dmasr & ETH_DMASR_TS) { - /* Data Transmitted.*/ - chSysLockFromIsr(); - chSemResetI(ÐD1.tdsem, 0); - chSysUnlockFromIsr(); - } - - CH_IRQ_EPILOGUE(); -} - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -211,74 +71,11 @@ CH_IRQ_HANDLER(ETH_IRQHandler) { * @notapi */ void mac_lld_init(void) { - unsigned i; - - macObjectInit(ÐD1); - ETHD1.link_up = FALSE; - - /* Descriptor tables are initialized in chained mode, note that the first - word is not initialized here but in mac_lld_start().*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes1 = STM32_RDES1_RCH | STM32_MAC_BUFFERS_SIZE; - rd[i].rdes2 = (uint32_t)rb[i]; - rd[i].rdes3 = (uint32_t)&rd[(i + 1) % STM32_MAC_RECEIVE_BUFFERS]; - } - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes1 = 0; - td[i].tdes2 = (uint32_t)tb[i]; - td[i].tdes3 = (uint32_t)&td[(i + 1) % STM32_MAC_TRANSMIT_BUFFERS]; - } - - /* Selection of the RMII or MII mode based on info exported by board.h.*/ -#if defined(STM32F10X_CL) -#if defined(BOARD_PHY_RMII) - AFIO->MAPR |= AFIO_MAPR_MII_RMII_SEL; -#else - AFIO->MAPR &= ~AFIO_MAPR_MII_RMII_SEL; -#endif -#elif defined(STM32F2XX) || defined(STM32F4XX) -#if defined(BOARD_PHY_RMII) - SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; -#else - SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; -#endif -#else -#error "unsupported STM32 platform for MAC driver" -#endif - - /* Reset of the MAC core.*/ - rccResetETH(); - - /* MAC clocks temporary activation.*/ - rccEnableETH(FALSE); - - /* PHY address setup.*/ -#if defined(BOARD_PHY_ADDRESS) - ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; -#else - mii_find_phy(ÐD1); -#endif - -#if defined(BOARD_PHY_RESET) - /* PHY board-specific reset procedure.*/ - BOARD_PHY_RESET(); -#else - /* PHY soft reset procedure.*/ - mii_write(ÐD1, MII_BMCR, BMCR_RESET); -#if defined(BOARD_PHY_RESET_DELAY) - halPolledDelay(BOARD_PHY_RESET_DELAY); -#endif - while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) - ; -#endif - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be started.*/ - mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); -#endif - /* MAC clocks stopped again.*/ - rccDisableETH(FALSE); +#if PLATFORM_MAC_USE_MAC1 + /* Driver initialization.*/ + macObjectInit(&MACD1); +#endif /* PLATFORM_MAC_USE_MAC1 */ } /** @@ -289,71 +86,17 @@ void mac_lld_init(void) { * @notapi */ void mac_lld_start(MACDriver *macp) { - unsigned i; - - /* Resets the state of all descriptors.*/ - for (i = 0; i < STM32_MAC_RECEIVE_BUFFERS; i++) - rd[i].rdes0 = STM32_RDES0_OWN; - macp->rxptr = (stm32_eth_rx_descriptor_t *)rd; - for (i = 0; i < STM32_MAC_TRANSMIT_BUFFERS; i++) - td[i].tdes0 = STM32_TDES0_TCH; - macp->txptr = (stm32_eth_tx_descriptor_t *)td; - - /* MAC clocks activation and commanded reset procedure.*/ - rccEnableETH(FALSE); - ETH->DMABMR |= ETH_DMABMR_SR; - while(ETH->DMABMR & ETH_DMABMR_SR) - ; - - /* ISR vector enabled.*/ - nvicEnableVector(ETH_IRQn, - CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY)); - -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power up mode.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); -#endif - - /* MAC configuration.*/ - ETH->MACFFR = 0; - ETH->MACFCR = 0; - ETH->MACVLANTR = 0; - - /* MAC address setup.*/ - if (macp->config->mac_address == NULL) - mac_lld_set_address(default_mac_address); - else - mac_lld_set_address(macp->config->mac_address); - - /* Transmitter and receiver enabled. - Note that the complete setup of the MAC is performed when the link - status is detected.*/ -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; -#else - ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; -#endif - /* DMA configuration: - Descriptor chains pointers.*/ - ETH->DMARDLAR = (uint32_t)rd; - ETH->DMATDLAR = (uint32_t)td; + if (macp->state == MAC_STOP) { + /* Enables the pehipheral.*/ +#if PLATFORM_MAC_USE_MAC1 + if (&MACD1 == macp) { - /* Enabling required interrupt sources.*/ - ETH->DMASR = ETH->DMASR; - ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; - - /* DMA general settings.*/ - ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_RDP_1Beat | ETH_DMABMR_PBL_1Beat; - - /* Transmit FIFO flush.*/ - ETH->DMAOMR = ETH_DMAOMR_FTF; - while (ETH->DMAOMR & ETH_DMAOMR_FTF) - ; + } +#endif /* PLATFORM_MAC_USE_MAC1 */ + } + /* Configures the peripheral.*/ - /* DMA final configuration and start.*/ - ETH->DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_TSF | - ETH_DMAOMR_ST | ETH_DMAOMR_SR; } /** @@ -365,23 +108,15 @@ void mac_lld_start(MACDriver *macp) { */ void mac_lld_stop(MACDriver *macp) { - if (macp->state != MAC_STOP) { -#if STM32_MAC_ETH1_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be restarted.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC and DMA stopped.*/ - ETH->MACCR = 0; - ETH->DMAOMR = 0; - ETH->DMAIER = 0; - ETH->DMASR = ETH->DMASR; + if (macp->state == MAC_ACTIVE) { + /* Resets the peripheral.*/ - /* MAC clocks stopped.*/ - rccDisableETH(FALSE); + /* Disables the peripheral.*/ +#if PLATFORM_MAC_USE_MAC1 + if (&MACD1 == macp) { - /* ISR vector disabled.*/ - nvicDisableVector(ETH_IRQn); + } +#endif /* PLATFORM_MAC_USE_MAC1 */ } } @@ -400,35 +135,9 @@ void mac_lld_stop(MACDriver *macp) { */ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, MACTransmitDescriptor *tdp) { - stm32_eth_tx_descriptor_t *tdes; - - if (!macp->link_up) - return RDY_TIMEOUT; - - chSysLock(); - - /* Get Current TX descriptor.*/ - tdes = macp->txptr; - - /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by - another thread.*/ - if (tdes->tdes0 & (STM32_TDES0_OWN | STM32_TDES0_LOCKED)) { - chSysUnlock(); - return RDY_TIMEOUT; - } - - /* Marks the current descriptor as locked using a reserved bit.*/ - tdes->tdes0 |= STM32_TDES0_LOCKED; - /* Next TX descriptor to use.*/ - macp->txptr = (stm32_eth_tx_descriptor_t *)tdes->tdes3; - - chSysUnlock(); - - /* Set the buffer size and configuration.*/ - tdp->offset = 0; - tdp->size = STM32_MAC_BUFFERS_SIZE; - tdp->physdesc = tdes; + (void)macp; + (void)tdp; return RDY_OK; } @@ -443,25 +152,8 @@ msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, */ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { - chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "mac_lld_release_transmit_descriptor(), #1", - "attempt to release descriptor already owned by DMA"); - - chSysLock(); - - /* Unlocks the descriptor and returns it to the DMA engine.*/ - tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) | - STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | - STM32_TDES0_TCH | STM32_TDES0_OWN; + (void)tdp; - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_TPS) == ETH_DMASR_TPS_Suspended) { - ETH->DMASR = ETH_DMASR_TBUS; - ETH->DMATPDR = ETH_DMASR_TBUS; /* Any value is OK.*/ - } - - chSysUnlock(); } /** @@ -477,41 +169,11 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { */ msg_t mac_lld_get_receive_descriptor(MACDriver *macp, MACReceiveDescriptor *rdp) { - stm32_eth_rx_descriptor_t *rdes; - - chSysLock(); - /* Get Current RX descriptor.*/ - rdes = macp->rxptr; + (void)macp; + (void)rdp; - /* Iterates through received frames until a valid one is found, invalid - frames are discarded.*/ - while (!(rdes->rdes0 & STM32_RDES0_OWN)) { - if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) -#if STM32_MAC_IP_CHECKSUM_OFFLOAD - && (rdes->rdes0 & STM32_RDES0_FT) - && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE)) -#endif - && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) { - /* Found a valid one.*/ - rdp->offset = 0; - rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4; - rdp->physdesc = rdes; - macp->rxptr = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - - chSysUnlock(); - return RDY_OK; - } - /* Invalid frame found, purging.*/ - rdes->rdes0 = STM32_RDES0_OWN; - rdes = (stm32_eth_rx_descriptor_t *)rdes->rdes3; - } - - /* Next descriptor to check.*/ - macp->rxptr = rdes; - - chSysUnlock(); - return RDY_TIMEOUT; + return RDY_OK; } /** @@ -525,22 +187,8 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp, */ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { - chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "mac_lld_release_receive_descriptor(), #1", - "attempt to release descriptor already owned by DMA"); - - chSysLock(); + (void)rdp; - /* Give buffer back to the Ethernet DMA.*/ - rdp->physdesc->rdes0 = STM32_RDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMASR & ETH_DMASR_RPS) == ETH_DMASR_RPS_Suspended) { - ETH->DMASR = ETH_DMASR_RBUS; - ETH->DMARPDR = ETH_DMASR_RBUS; /* Any value is OK.*/ - } - - chSysUnlock(); } /** @@ -554,62 +202,10 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) { * @notapi */ bool_t mac_lld_poll_link_status(MACDriver *macp) { - uint32_t maccr, bmsr, bmcr; - - maccr = ETH->MACCR; - - /* PHY CR and SR registers read.*/ - (void)mii_read(macp, MII_BMSR); - bmsr = mii_read(macp, MII_BMSR); - bmcr = mii_read(macp, MII_BMCR); - - /* Check on auto-negotiation mode.*/ - if (bmcr & BMCR_ANENABLE) { - uint32_t lpa; - - /* Auto-negotiation must be finished without faults and link established.*/ - if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != - (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) - return macp->link_up = FALSE; - - /* Auto-negotiation enabled, checks the LPA register.*/ - lpa = mii_read(macp, MII_LPA); - - /* Check on link speed.*/ - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (lpa & (LPA_10FULL | LPA_100FULL)) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - else { - /* Link must be established.*/ - if (!(bmsr & BMSR_LSTATUS)) - return macp->link_up = FALSE; - - /* Check on link speed.*/ - if (bmcr & BMCR_SPEED100) - maccr |= ETH_MACCR_FES; - else - maccr &= ~ETH_MACCR_FES; - - /* Check on link mode.*/ - if (bmcr & BMCR_FULLDPLX) - maccr |= ETH_MACCR_DM; - else - maccr &= ~ETH_MACCR_DM; - } - /* Changes the mode in the MAC.*/ - ETH->MACCR = maccr; + (void)macp; - /* Returns the link status.*/ - return macp->link_up = TRUE; + return FALSE; } /** @@ -630,17 +226,9 @@ size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, uint8_t *buf, size_t size) { - chDbgAssert(!(tdp->physdesc->tdes0 & STM32_TDES0_OWN), - "mac_lld_write_transmit_descriptor(), #1", - "attempt to write descriptor already owned by DMA"); - - if (size > tdp->size - tdp->offset) - size = tdp->size - tdp->offset; + (void)tdp; + (void)buf; - if (size > 0) { - memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); - tdp->offset += size; - } return size; } @@ -661,17 +249,9 @@ size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, uint8_t *buf, size_t size) { - chDbgAssert(!(rdp->physdesc->rdes0 & STM32_RDES0_OWN), - "mac_lld_read_receive_descriptor(), #1", - "attempt to read descriptor already owned by DMA"); + (void)rdp; + (void)buf; - if (size > rdp->size - rdp->offset) - size = rdp->size - rdp->offset; - - if (size > 0) { - memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); - rdp->offset += size; - } return size; } @@ -701,12 +281,10 @@ uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, size_t size, size_t *sizep) { - if (tdp->offset == 0) { - *sizep = tdp->size; - tdp->offset = size; - return (uint8_t *)tdp->physdesc->tdes2; - } - *sizep = 0; + (void)tdp; + (void)size; + (void)sizep; + return NULL; } @@ -727,13 +305,9 @@ uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, size_t *sizep) { - if (rdp->size > 0) { - *sizep = rdp->size; - rdp->offset = rdp->size; - rdp->size = 0; - return (uint8_t *)rdp->physdesc->rdes2; - } - *sizep = 0; + (void)rdp; + (void)sizep; + return NULL; } #endif /* MAC_USE_ZERO_COPY */ diff --git a/os/hal/templates/mac_lld.h b/os/hal/templates/mac_lld.h index cb6a6cd8b..cd5854e80 100644 --- a/os/hal/templates/mac_lld.h +++ b/os/hal/templates/mac_lld.h @@ -44,6 +44,19 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ +/** + * @brief MAC driver enable switch. + * @details If set to @p TRUE the support for MAC1 is included. + */ +#if !defined(PLATFORM_MAC_USE_MAC1) || defined(__DOXYGEN__) +#define PLATFORM_MAC_USE_MAC1 FALSE +#endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -130,7 +143,7 @@ typedef struct { /* External declarations. */ /*===========================================================================*/ -#if !defined(__DOXYGEN__) +#if PLATFORM_MAC_USE_MAC1 && !defined(__DOXYGEN__) extern MACDriver ETHD1; #endif diff --git a/os/hal/templates/meta/driver_lld.c b/os/hal/templates/meta/driver_lld.c index 95d1b1063..91ff4a0b6 100644 --- a/os/hal/templates/meta/driver_lld.c +++ b/os/hal/templates/meta/driver_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief XXX1 driver identifier.*/ +/** + * @brief XXX1 driver identifier. + */ #if PLATFORM_XXX_USE_XXX1 || defined(__DOXYGEN__) XXXDriver XXXD1; #endif diff --git a/os/hal/templates/pal_lld.c b/os/hal/templates/pal_lld.c index 10e2ae482..212e3359d 100644 --- a/os/hal/templates/pal_lld.c +++ b/os/hal/templates/pal_lld.c @@ -65,6 +65,8 @@ */ void _pal_lld_init(const PALConfig *config) { + (void)config; + } /** @@ -82,6 +84,10 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) { + (void)port; + (void)mask; + (void)mode; + } #endif /* HAL_USE_PAL */ diff --git a/os/hal/templates/sdc_lld.c b/os/hal/templates/sdc_lld.c index 2a7aafff1..0a6185c63 100644 --- a/os/hal/templates/sdc_lld.c +++ b/os/hal/templates/sdc_lld.c @@ -39,7 +39,9 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief SDCD1 driver identifier.*/ +/** + * @brief SDCD1 driver identifier. + */ #if PLATFORM_SDC_USE_SDC1 || defined(__DOXYGEN__) SDCDriver SDCD1; #endif @@ -143,7 +145,6 @@ void sdc_lld_stop_clk(SDCDriver *sdcp) { * @notapi */ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; (void)sdcp; @@ -172,6 +173,8 @@ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { (void)sdcp; + (void)cmd; + (void)arg; } /** @@ -191,8 +194,13 @@ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { */ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, uint32_t *resp) { - - return CH_SUCCESS; + + (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; + + return CH_SUCCESS; } /** @@ -213,6 +221,9 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, uint32_t *resp) { (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; return CH_SUCCESS; } @@ -235,6 +246,9 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, uint32_t *resp) { (void)sdcp; + (void)cmd; + (void)arg; + (void)resp; return CH_SUCCESS; } @@ -256,6 +270,11 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, uint8_t *buf, uint32_t n) { + (void)sdcp; + (void)startblk; + (void)buf; + (void)n; + return CH_SUCCESS; } @@ -276,6 +295,11 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, const uint8_t *buf, uint32_t n) { + (void)sdcp; + (void)startblk; + (void)buf; + (void)n; + return CH_SUCCESS; } -- cgit v1.2.3