From c2994bdb33024b71f3ac0b4283994715ce6eb563 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Thu, 4 Jan 2018 11:13:44 +0000 Subject: Various fixes, H7 SPI does not work yet. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11220 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'os/hal') diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c index 936537337..71dd11702 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c @@ -525,6 +525,7 @@ void spi_lld_start(SPIDriver *spip) { /* Configuration-specific DMA setup.*/ dsize = (spip->config->cfg2 & SPI_CFG1_DSIZE_Msk) + 1U; cfg1 = spip->config->cfg1 | SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN; + cfg1 &= ~SPI_CFG1_FTHLV_Msk; if (dsize <= 8U) { /* Frame width is between 4 and 8 bits.*/ spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | @@ -561,7 +562,7 @@ void spi_lld_start(SPIDriver *spip) { spip->spi->CR1 = SPI_CR1_MASRX; spip->spi->CR2 = 0U; spip->spi->CFG1 = cfg1; - spip->spi->CFG2 = spip->config->cfg2 | SPI_CFG2_MASTER; + spip->spi->CFG2 = (spip->config->cfg2 | SPI_CFG2_MASTER) & ~SPI_CFG2_COMM_Msk; spip->spi->IER = SPI_IER_OVRIE; spip->spi->IFCR = 0xFFFFFFFFU; spip->spi->CR1 |= SPI_CR1_SPE; -- cgit v1.2.3