From abbc1097778c5718dd314af045f40b037ccb4cb5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Aug 2013 12:33:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6188 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/I2Cv2/i2c_lld.h | 8 -- os/hal/platforms/STM32/SPIv2/spi_lld.h | 9 -- os/hal/platforms/STM32/USARTv2/uart_lld.h | 8 -- os/hal/platforms/STM32F0xx/hal_lld.c | 8 -- os/hal/platforms/STM32F0xx/hal_lld.h | 3 +- os/hal/platforms/STM32F0xx/platform.mk | 7 +- os/hal/platforms/STM32F0xx/stm32_dma.c | 29 ++-- os/hal/platforms/STM32F0xx/stm32_registry.h | 210 +++++++++++----------------- os/hal/platforms/STM32F30x/hal_lld.c | 11 -- 9 files changed, 101 insertions(+), 192 deletions(-) (limited to 'os/hal') diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h index a2687cbc8..ca654d582 100644 --- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.h +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.h @@ -132,14 +132,6 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -/* TODO: Move the following DMA settings in the STM32F0XX registry.*/ -#if defined(STM32F0XX) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif - /* TODO: Move the following DMA settings in the STM32F37X registry.*/ #if defined(STM32F37X) #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.h b/os/hal/platforms/STM32/SPIv2/spi_lld.h index ceac42b2c..07123df12 100644 --- a/os/hal/platforms/STM32/SPIv2/spi_lld.h +++ b/os/hal/platforms/STM32/SPIv2/spi_lld.h @@ -124,15 +124,6 @@ #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") #endif -/* TODO: Move the following DMA settings in the STM32F0XX registry.*/ -#if defined(STM32F0XX) -/* Fixed values for STM32F0xx devices.*/ -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#endif /* defined(STM32F0XX) */ - /* TODO: Move the following DMA settings in the STM32F37X registry.*/ #if defined(STM32F37X) /* Fixed values for STM32F3xx devices.*/ diff --git a/os/hal/platforms/STM32/USARTv2/uart_lld.h b/os/hal/platforms/STM32/USARTv2/uart_lld.h index 6b4393e96..32b1f6e47 100644 --- a/os/hal/platforms/STM32/USARTv2/uart_lld.h +++ b/os/hal/platforms/STM32/USARTv2/uart_lld.h @@ -126,14 +126,6 @@ #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") #endif -#if defined(STM32F0XX) -/* Fixed values for STM32F0xx devices.*/ -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#endif /* defined(STM32F0XX) */ - #if defined(STM32F37X) /* Fixed values for STM32F3xx devices.*/ #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index debc51ea3..09ab62923 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /*===========================================================================*/ @@ -103,13 +102,6 @@ void hal_lld_init(void) { rccResetAPB1(0xFFFFFFFF); rccResetAPB2(~RCC_APB2RSTR_DBGMCURST); - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - /* PWR clock enabled.*/ rccEnablePWRInterface(FALSE); diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index dcff57a5c..c7238de56 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -761,7 +761,8 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 ISR, DMA and RCC helpers.*/ +/* Various helpers.*/ +#include "nvic.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk index 8e49a2e86..e54e4e0c7 100644 --- a/os/hal/platforms/STM32F0xx/platform.mk +++ b/os/hal/platforms/STM32F0xx/platform.mk @@ -1,5 +1,6 @@ # List of all the STM32F0xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx/nvic.c \ + ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \ @@ -10,11 +11,13 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ + ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/st_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \ ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \ +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx \ + ${CHIBIOS}/os/hal/platforms/STM32F0xx \ ${CHIBIOS}/os/hal/platforms/STM32 \ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \ ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \ diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c index 2305d952d..623c9d11b 100644 --- a/os/hal/platforms/STM32F0xx/stm32_dma.c +++ b/os/hal/platforms/STM32F0xx/stm32_dma.c @@ -29,7 +29,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /* The following macro is only defined if some driver requiring DMA services @@ -109,17 +108,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; * * @isr */ -CH_IRQ_HANDLER(Vector64) { +OSAL_IRQ_HANDLER(Vector64) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[0].dma_func) dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -127,10 +126,10 @@ CH_IRQ_HANDLER(Vector64) { * * @isr */ -CH_IRQ_HANDLER(Vector68) { +OSAL_IRQ_HANDLER(Vector68) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); /* Check on channel 2.*/ flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; @@ -148,7 +147,7 @@ CH_IRQ_HANDLER(Vector68) { dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); } - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -156,10 +155,10 @@ CH_IRQ_HANDLER(Vector68) { * * @isr */ -CH_IRQ_HANDLER(Vector6C) { +OSAL_IRQ_HANDLER(Vector6C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); /* Check on channel 4.*/ flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; @@ -177,7 +176,7 @@ CH_IRQ_HANDLER(Vector6C) { dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); } - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /*===========================================================================*/ @@ -229,7 +228,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, stm32_dmaisr_t func, void *param) { - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + osalDbgCheck(dmastp != NULL); /* Checks if the stream is already taken.*/ if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) @@ -250,7 +249,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, /* Enables the associated IRQ vector if a callback is defined.*/ if (func != NULL) - nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority)); + nvicEnableVector(dmastp->vector, priority); return FALSE; } @@ -270,11 +269,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, */ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + osalDbgCheck(dmastp != NULL); /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); + osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "not allocated"); /* Disables the associated IRQ vector.*/ nvicDisableVector(dmastp->vector); diff --git a/os/hal/platforms/STM32F0xx/stm32_registry.h b/os/hal/platforms/STM32F0xx/stm32_registry.h index ccef92730..5139beeaf 100644 --- a/os/hal/platforms/STM32F0xx/stm32_registry.h +++ b/os/hal/platforms/STM32F0xx/stm32_registry.h @@ -34,163 +34,113 @@ * @{ */ /* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \ - STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_ADC1_DMA_CHN 0x00000000 -#define STM32_HAS_ADC2 FALSE -#define STM32_ADC2_DMA_MSK 0x00000000 -#define STM32_ADC2_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC3 FALSE -#define STM32_ADC3_DMA_MSK 0x00000000 -#define STM32_ADC3_DMA_CHN 0x00000000 - -#define STM32_HAS_ADC4 FALSE -#define STM32_ADC4_DMA_MSK 0x00000000 -#define STM32_ADC4_DMA_CHN 0x00000000 +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE /* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE /* DAC attributes.*/ -#define STM32_HAS_DAC TRUE +#define STM32_HAS_DAC TRUE /* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE /* ETH attributes.*/ -#define STM32_HAS_ETH FALSE +#define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 28 +#define STM32_EXTI_NUM_CHANNELS 28 /* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE /* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_I2C3 FALSE /* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTC_HAS_SUBSECONDS FALSE -#define STM32_RTC_IS_CALENDAR TRUE +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE /* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE +#define STM32_HAS_SDIO FALSE /* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI3 FALSE /* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM1 TRUE +#define STM32_HAS_TIM2 TRUE +#define STM32_HAS_TIM3 TRUE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 TRUE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 TRUE +#define STM32_HAS_TIM15 TRUE +#define STM32_HAS_TIM16 TRUE +#define STM32_HAS_TIM17 TRUE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE /* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE /* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB TRUE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE /** @} */ #endif /* _STM32_REGISTRY_H_ */ diff --git a/os/hal/platforms/STM32F30x/hal_lld.c b/os/hal/platforms/STM32F30x/hal_lld.c index 46ca8a7f9..4521231d5 100644 --- a/os/hal/platforms/STM32F30x/hal_lld.c +++ b/os/hal/platforms/STM32F30x/hal_lld.c @@ -102,17 +102,6 @@ void hal_lld_init(void) { rccResetAPB1(0xFFFFFFFF); rccResetAPB2(0xFFFFFFFF); - /* SysTick initialization using the system clock.*/ -// SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; -// SysTick->VAL = 0; -// SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | -// SysTick_CTRL_ENABLE_Msk | -// SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ -// SCS_DEMCR |= SCS_DEMCR_TRCENA; -// DWT_CTRL |= DWT_CTRL_CYCCNTENA; - /* PWR clock enabled.*/ rccEnablePWRInterface(FALSE); -- cgit v1.2.3