From 7dc3e6a0f0d660aa2695f46ef4e6ccac4f6553de Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 4 Jun 2013 12:11:56 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5812
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC564Axx/platform.mk        |  2 ++
 os/hal/platforms/SPC564Axx/spc564a_registry.h | 34 +++++++++++++++++++++++++++
 2 files changed, 36 insertions(+)

(limited to 'os/hal')

diff --git a/os/hal/platforms/SPC564Axx/platform.mk b/os/hal/platforms/SPC564Axx/platform.mk
index 01b8e528e..6abcecaec 100644
--- a/os/hal/platforms/SPC564Axx/platform.mk
+++ b/os/hal/platforms/SPC564Axx/platform.mk
@@ -1,5 +1,6 @@
 # List of all the SPC564Axx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c \
@@ -7,6 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC564Axx/hal_lld.c \
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC564Axx \
+              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/EQADC_v1 \
               ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h
index e23cf4281..5002b9ac7 100644
--- a/os/hal/platforms/SPC564Axx/spc564a_registry.h
+++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h
@@ -33,6 +33,40 @@
  * @name    SPC564Axx capabilities
  * @{
  */
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0                      FALSE
+#define SPC5_HAS_DSPI1                      TRUE
+#define SPC5_HAS_DSPI2                      TRUE
+#define SPC5_HAS_DSPI3                      TRUE
+#define SPC5_DSPI_FIFO_DEPTH                16
+#define SPC5_DSPI1_TX1_DMA_DEV_ID           12
+#define SPC5_DSPI1_TX2_DMA_DEV_ID           24
+#define SPC5_DSPI1_RX_DMA_DEV_ID            13
+#define SPC5_DSPI2_TX1_DMA_DEV_ID           14
+#define SPC5_DSPI2_TX2_DMA_DEV_ID           25
+#define SPC5_DSPI2_RX_DMA_DEV_ID            15
+#define SPC5_DSPI3_TX1_DMA_DEV_ID           16
+#define SPC5_DSPI3_TX2_DMA_DEV_ID           26
+#define SPC5_DSPI3_RX_DMA_DEV_ID            17
+#define SPC5_DSPI1_EOQF_HANDLER             vector132
+#define SPC5_DSPI1_EOQF_NUMBER              132
+#define SPC5_DSPI1_TFFF_HANDLER             vector133
+#define SPC5_DSPI1_TFFF_NUMBER              133
+#define SPC5_DSPI2_EOQF_HANDLER             vector137
+#define SPC5_DSPI2_EOQF_NUMBER              137
+#define SPC5_DSPI2_TFFF_HANDLER             vector138
+#define SPC5_DSPI2_TFFF_NUMBER              138
+#define SPC5_DSPI3_EOQF_HANDLER             vector142
+#define SPC5_DSPI3_EOQF_NUMBER              142
+#define SPC5_DSPI3_TFFF_HANDLER             vector143
+#define SPC5_DSPI3_TFFF_NUMBER              143
+#define SPC5_DSPI1_ENABLE_CLOCK()
+#define SPC5_DSPI1_DISABLE_CLOCK()
+#define SPC5_DSPI2_ENABLE_CLOCK()
+#define SPC5_DSPI2_DISABLE_CLOCK()
+#define SPC5_DSPI3_ENABLE_CLOCK()
+#define SPC5_DSPI3_DISABLE_CLOCK()
+
 /* eDMA attributes.*/
 #define SPC5_HAS_EDMA                       TRUE
 #define SPC5_EDMA_NCHANNELS                 64
-- 
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