From 74eeb190672359c4a53ad4805f713008c9bbb9ca Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 6 Jul 2012 12:44:10 +0000
Subject: I2C. Additional runtime checks of clock divider.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4408 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/I2Cv1/i2c_lld.c | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

(limited to 'os/hal')

diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
index bf6ef05cc..0d6d4a651 100644
--- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
+++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c
@@ -207,11 +207,14 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
                 "Invalid standard mode duty cycle");
 
     /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
+    chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
+                "i2c_lld_set_clock(), #2",
+                "PCLK1 must be divided without remainder");
     clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
 
-    /* Clock divider values under four are not allowed.*/
-    if (clock_div < 0x04)
-      clock_div = 0x04;
+    chDbgAssert(clock_div < 0x04,
+                "i2c_lld_set_clock(), #3",
+                "Clock divider less then 0x04 not allowed");
     regCCR |= (clock_div & I2C_CCR_CCR);
 
     /* Sets the Maximum Rise Time for standard mode.*/
@@ -220,21 +223,28 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
   else if (clock_speed <= 400000) {
     /* Configure clock_div in fast mode.*/
     chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9),
-                "i2c_lld_set_clock(), #2",
+                "i2c_lld_set_clock(), #4",
                 "Invalid fast mode duty cycle");
 
     if (duty == FAST_DUTY_CYCLE_2) {
       /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
+      chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
+                  "i2c_lld_set_clock(), #5",
+                  "PCLK1 must be divided without remainder");
       clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
     }
     else if (duty == FAST_DUTY_CYCLE_16_9) {
       /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
+      chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
+                  "i2c_lld_set_clock(), #6",
+                  "PCLK1 must be divided without remainder");
       clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
       regCCR |= I2C_CCR_DUTY;
     }
-    /* Clock divider values under one are not allowed.*/
-    if (clock_div < 0x01)
-      clock_div = 0x01;
+
+    chDbgAssert(clock_div < 0x01,
+                    "i2c_lld_set_clock(), #7",
+                    "Clock divider less then 0x04 not allowed");
     regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
 
     /* Sets the Maximum Rise Time for fast mode.*/
@@ -242,7 +252,7 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
   }
 
   chDbgAssert((clock_div <= I2C_CCR_CCR),
-              "i2c_lld_set_clock(), #3", "the selected clock is too low");
+              "i2c_lld_set_clock(), #8", "the selected clock is too low");
 
   dp->CCR = regCCR;
 }
-- 
cgit v1.2.3