From 6dc59bdf42a4342127dfbef2c1284bf544295a78 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 May 2013 09:20:30 +0000 Subject: ICU support for STM32 TIM9 unit. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5673 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/icu_lld.c | 52 +++++++++++++++- os/hal/platforms/STM32/icu_lld.h | 32 +++++++++- os/hal/platforms/STM32F4xx/stm32_rcc.h | 110 +-------------------------------- os/hal/platforms/STM32L1xx/stm32_isr.h | 2 + os/hal/platforms/STM32L1xx/stm32_rcc.h | 27 ++++++++ 5 files changed, 112 insertions(+), 111 deletions(-) (limited to 'os/hal') diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index ccf70bb70..2e3c4334b 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -87,6 +87,14 @@ ICUDriver ICUD5; ICUDriver ICUD8; #endif +/** + * @brief ICUD9 driver identifier. + * @note The driver ICUD9 allocates the timer TIM9 when enabled. + */ +#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__) +ICUDriver ICUD9; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -297,6 +305,28 @@ CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { } #endif /* STM32_ICU_USE_TIM8 */ +#if STM32_ICU_USE_TIM9 +#if !defined(STM32_TIM9_HANDLER) +#error "STM32_TIM9_HANDLER not defined" +#endif +/** + * @brief TIM9 interrupt handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { + + CH_IRQ_PROLOGUE(); + + icu_lld_serve_interrupt(&ICUD9); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_ICU_USE_TIM9 */ + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -343,6 +373,12 @@ void icu_lld_init(void) { icuObjectInit(&ICUD8); ICUD8.tim = STM32_TIM8; #endif + +#if STM32_ICU_USE_TIM9 + /* Driver initialization.*/ + icuObjectInit(&ICUD9); + ICUD9.tim = STM32_TIM9; +#endif } /** @@ -399,7 +435,6 @@ void icu_lld_start(ICUDriver *icup) { icup->clock = STM32_TIMCLK1; } #endif - #if STM32_ICU_USE_TIM5 if (&ICUD5 == icup) { rccEnableTIM5(FALSE); @@ -419,6 +454,15 @@ void icu_lld_start(ICUDriver *icup) { CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY)); icup->clock = STM32_TIMCLK2; } +#endif +#if STM32_ICU_USE_TIM9 + if (&ICUD9 == icup) { + rccEnableTIM9(FALSE); + rccResetTIM9(); + nvicEnableVector(STM32_TIM9_NUMBER, + CORTEX_PRIORITY_MASK(STM32_ICU_TIM9_IRQ_PRIORITY)); + icup->clock = STM32_TIMCLK1; + } #endif } else { @@ -540,6 +584,12 @@ void icu_lld_stop(ICUDriver *icup) { nvicDisableVector(STM32_TIM8_CC_NUMBER); rccDisableTIM8(FALSE); } +#endif +#if STM32_ICU_USE_TIM9 + if (&ICUD9 == icup) { + nvicDisableVector(STM32_TIM9_NUMBER); + rccDisableTIM9(FALSE); + } #endif } } diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index 90d401969..ee5f313f3 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -93,6 +93,15 @@ #define STM32_ICU_USE_TIM8 FALSE #endif +/** + * @brief ICUD9 driver enable switch. + * @details If set to @p TRUE the support for ICUD9 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ICU_USE_TIM9) || defined(__DOXYGEN__) +#define STM32_ICU_USE_TIM9 FALSE +#endif + /** * @brief ICUD1 interrupt priority level setting. */ @@ -134,6 +143,13 @@ #if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ICU_TIM8_IRQ_PRIORITY 7 #endif + +/** + * @brief ICUD9 interrupt priority level setting. + */ +#if !defined(STM32_ICU_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#endif /** @} */ /*===========================================================================*/ @@ -164,9 +180,14 @@ #error "TIM8 not present in the selected device" #endif +#if STM32_ICU_USE_TIM9 && !STM32_HAS_TIM9 +#error "TIM9 not present in the selected device" +#endif + #if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \ !STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \ - !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 + !STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8 && \ + !STM32_ICU_USE_TIM9 #error "ICU driver activated but no TIM peripheral assigned" #endif @@ -200,6 +221,11 @@ #error "Invalid IRQ priority assigned to TIM8" #endif +#if STM32_ICU_USE_TIM9 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TIM9" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -355,6 +381,10 @@ extern ICUDriver ICUD5; extern ICUDriver ICUD8; #endif +#if STM32_ICU_USE_TIM9 && !defined(__DOXYGEN__) +extern ICUDriver ICUD9; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index 7235f2caf..d87bc2ab2 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -970,23 +970,6 @@ */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) -/** - * @brief Disables the TIM9 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Resets the TIM8 peripheral. - * - * @api - */ -#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) - /** * @brief Enables the TIM89peripheral clock. * @note The @p lp parameter is ignored in this family. @@ -997,98 +980,6 @@ */ #define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) -/** - * @brief Enables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Disables the TIM11 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Resets the TIM11 peripheral. - * - * @api - */ -#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) - -/** - * @brief Enables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Disables the TIM12 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) - -/** - * @brief Resets the TIM12 peripheral. - * - * @api - */ -#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) - -/** - * @brief Enables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Disables the TIM14 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) - -/** - * @brief Resets the TIM14 peripheral. - * - * @api - */ -#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) -/** @} */ - -/** - * @brief Enables the TIM9 peripheral clock. - * @note The @p lp parameter is ignored in this family. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) - /** * @brief Disables the TIM9 peripheral clock. * @note The @p lp parameter is ignored in this family. @@ -1186,6 +1077,7 @@ * @api */ #define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) +/** @} */ /** * @name USART/UART peripherals specific RCC operations diff --git a/os/hal/platforms/STM32L1xx/stm32_isr.h b/os/hal/platforms/STM32L1xx/stm32_isr.h index 034ab2205..d90d28c0b 100644 --- a/os/hal/platforms/STM32L1xx/stm32_isr.h +++ b/os/hal/platforms/STM32L1xx/stm32_isr.h @@ -39,10 +39,12 @@ #define STM32_TIM2_HANDLER TIM2_IRQHandler #define STM32_TIM3_HANDLER TIM3_IRQHandler #define STM32_TIM4_HANDLER TIM4_IRQHandler +#define STM32_TIM9_HANDLER TIM9_IRQHandler #define STM32_TIM2_NUMBER TIM2_IRQn #define STM32_TIM3_NUMBER TIM3_IRQn #define STM32_TIM4_NUMBER TIM4_IRQn +#define STM32_TIM9_NUMBER TIM9_IRQn /* * USART units. diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index 5155eb340..5340b9e15 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -452,6 +452,33 @@ * @api */ #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM89peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) /** @} */ /** -- cgit v1.2.3