From 577f267dda280e46805275fca1722bf5dd112414 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 15 Jul 2015 12:47:29 +0000 Subject: Fixed bug #617. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8102 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32L0xx/hal_lld.h | 8 ++++---- os/hal/ports/STM32/STM32L1xx/hal_lld.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'os/hal') diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index 1d707ccaa..6c726b96e 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -97,9 +97,9 @@ #define STM32_PLS_EXT (7 << 5) /**< PVD level 7. */ #define STM32_VOS_MASK (3 << 11) /**< VOS field mask. */ -#define STM32_VOS_RANGE1 (1 << 11) /**< VOS level 1.8 volts. */ -#define STM32_VOS_RANGE2 (2 << 11) /**< VOS level 1.5 volts. */ -#define STM32_VOS_RANGE3 (3 << 11) /**< VOS level 1.2 volts. */ +#define STM32_VOS_1P8 (1 << 11) /**< VOS level 1.8 volts. */ +#define STM32_VOS_1P5 (2 << 11) /**< VOS level 1.5 volts. */ +#define STM32_VOS_1P2 (3 << 11) /**< VOS level 1.2 volts. */ /** @} */ /** @@ -316,7 +316,7 @@ /** * @brief Enables or disables the LSE clock source. */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) #define STM32_LSE_ENABLED FALSE #endif diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h index f3e9bfd08..93f6e02bc 100644 --- a/os/hal/ports/STM32/STM32L1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h @@ -244,7 +244,7 @@ /** * @brief Enables or disables the LSE clock source. */ -#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) #define STM32_LSE_ENABLED FALSE #endif -- cgit v1.2.3