From 4b2705efbffc4849583f37984762388be5a01b21 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 2 Jan 2014 15:11:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6601 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/boards/ST_STM32F0_DISCOVERY/board.h | 2 +- os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg | 1 + os/hal/ports/STM32/GPIOv2/pal_lld.c | 19 +- os/hal/ports/STM32/GPIOv2/pal_lld.h | 18 +- os/hal/ports/STM32F0xx/hal_lld.h | 23 +- os/hal/ports/STM32F0xx/stm32_registry.h | 255 +++++++++++++++++++++ 6 files changed, 307 insertions(+), 11 deletions(-) (limited to 'os/hal') diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h index be690cc6a..578aa49b7 100644 --- a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h @@ -45,7 +45,7 @@ #define STM32_HSE_BYPASS /* - * MCU type as defined in the ST header file stm32f0xx.h. + * MCU type as defined in the ST header. */ #define STM32F0XX_MD diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg index 3773f03d1..ec85130c7 100644 --- a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg +++ b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg @@ -10,6 +10,7 @@ ST STM32F0-Discovery ST_STM32F0_DISCOVERY + STM32F0XX_MD diff --git a/os/hal/ports/STM32/GPIOv2/pal_lld.c b/os/hal/ports/STM32/GPIOv2/pal_lld.c index 48290ae9c..957e51c61 100644 --- a/os/hal/ports/STM32/GPIOv2/pal_lld.c +++ b/os/hal/ports/STM32/GPIOv2/pal_lld.c @@ -35,21 +35,29 @@ RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN) #define AHB_LPEN_MASK AHB_EN_MASK -#elif defined(STM32F0XX_LD) || defined(STM32F0XX_MD) + +#elif defined(STM32F030) || defined(STM32F0XX_MD) #define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) + +#elif defined(STM32F0XX_LD) +#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN) + #elif defined(STM32F2XX) #define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \ RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ RCC_AHB1ENR_GPIOIEN) + #define AHB1_LPEN_MASK AHB1_EN_MASK #elif defined(STM32F30X) || defined(STM32F37X) #define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN) + #elif defined(STM32F4XX) #define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \ @@ -57,6 +65,7 @@ RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \ RCC_AHB1ENR_GPIOIEN) #define AHB1_LPEN_MASK AHB1_EN_MASK + #else #error "missing or unsupported platform for GPIOv2 PAL driver" #endif @@ -120,10 +129,18 @@ void _pal_lld_init(const PALConfig *config) { /* * Initial GPIO setup. */ +#if STM32_HAS_GPIOA initgpio(GPIOA, &config->PAData); +#endif +#if STM32_HAS_GPIOB initgpio(GPIOB, &config->PBData); +#endif +#if STM32_HAS_GPIOC initgpio(GPIOC, &config->PCData); +#endif +#if STM32_HAS_GPIOD initgpio(GPIOD, &config->PDData); +#endif #if STM32_HAS_GPIOE initgpio(GPIOE, &config->PEData); #endif diff --git a/os/hal/ports/STM32/GPIOv2/pal_lld.h b/os/hal/ports/STM32/GPIOv2/pal_lld.h index ae20a4a70..42b9ba02d 100644 --- a/os/hal/ports/STM32/GPIOv2/pal_lld.h +++ b/os/hal/ports/STM32/GPIOv2/pal_lld.h @@ -215,31 +215,39 @@ typedef struct { * or whole ports can be reprogrammed at later time. */ typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) /** @brief Port A setup data.*/ stm32_gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) /** @brief Port B setup data.*/ stm32_gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) /** @brief Port C setup data.*/ stm32_gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) /** @brief Port D setup data.*/ stm32_gpio_setup_t PDData; -#if STM32_HAS_GPIOE +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) /** @brief Port E setup data.*/ stm32_gpio_setup_t PEData; #endif -#if STM32_HAS_GPIOF +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) /** @brief Port F setup data.*/ stm32_gpio_setup_t PFData; #endif -#if STM32_HAS_GPIOG +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) /** @brief Port G setup data.*/ stm32_gpio_setup_t PGData; #endif -#if STM32_HAS_GPIOH +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) /** @brief Port H setup data.*/ stm32_gpio_setup_t PHData; #endif -#if STM32_HAS_GPIOI +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) /** @brief Port I setup data.*/ stm32_gpio_setup_t PIData; #endif diff --git a/os/hal/ports/STM32F0xx/hal_lld.h b/os/hal/ports/STM32F0xx/hal_lld.h index 99fb5bd28..044b13a37 100644 --- a/os/hal/ports/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32F0xx/hal_lld.h @@ -26,8 +26,9 @@ * - STM32_HSE_BYPASS (optionally). * . * One of the following macros must also be defined: - * - STM32F0XX_LD for Low Density Entry Level devices. - * - STM32F0XX_MD for Medium Density Entry Level devices. + * - STM32F030 for Value Line devices. + * - STM32F0XX_LD for Low Density devices. + * - STM32F0XX_MD for Medium Density devices. * . * * @addtogroup HAL @@ -44,10 +45,24 @@ /*===========================================================================*/ /** - * @name Platform identification + * @name Platform identification macros * @{ */ -#define PLATFORM_NAME "STM32F05x Entry Level" +#if defined(STM32F0XX_MD) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F051xx/F061xx Entry Level Medium Density devices" +#define STM32F0XX + +#elif defined(STM32F0XX_LD) +#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Low Density devices" +#define STM32F0XX + +#elif defined(STM32F030) +#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Value Line devices" +#define STM32F0XX + +#else +#error "STM32F0xx device not specified" +#endif /** @} */ /** diff --git a/os/hal/ports/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32F0xx/stm32_registry.h index 599e7acfe..4f738859b 100644 --- a/os/hal/ports/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32F0xx/stm32_registry.h @@ -33,6 +33,8 @@ * @name STM32F0xx capabilities * @{ */ +#if defined(STM32F0XX_MD) || defined(__DOXYGEN__) + /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 FALSE @@ -164,6 +166,259 @@ #define STM32_HAS_USB TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE + +#elif defined(STM32F0XX_LD) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 28 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD FALSE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C3 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 2 + +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM15 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_USART2 FALSE +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#else /* STM32F030 */ + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_CHANNELS 28 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_I2C3 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS FALSE +#define STM32_RTC_IS_CALENDAR TRUE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 2 + +#define STM32_HAS_TIM2 FALSE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +#endif /* STM32F030 */ + /** @} */ #endif /* _STM32_REGISTRY_H_ */ -- cgit v1.2.3