From 3bbaa571d416b04e88c3ca7fea276d750eee9c96 Mon Sep 17 00:00:00 2001
From: Rocco Marco Guglielmi <roccomarco.guglielmi@live.com>
Date: Sat, 4 Jun 2016 16:01:07 +0000
Subject: Improved PLLSAI for STM32F446xx and STM32F469xx/79xx. Updated
 mcuconf.h for STM32F446xx and STM32F469xx/79xx. Added Clock 48 selector.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9575 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32F4xx/hal_lld.c |  4 ++--
 os/hal/ports/STM32/STM32F4xx/hal_lld.h | 24 ++++++++++++++++++++++--
 2 files changed, 24 insertions(+), 4 deletions(-)

(limited to 'os/hal')

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 91583f263..91e3c1367 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -238,8 +238,8 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLLSAI
   /* PLLSAI activation.*/
-  RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ |
-                    STM32_PLLSAIP;
+  RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
+                    STM32_PLLSAIQ | STM32_PLLSAIM;
   
   RCC->CR |= RCC_CR_PLLSAION;
 
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 57445ed73..526a4ce1d 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -838,6 +838,16 @@
 #define STM32_PLLSAIN_VALUE         192
 #endif
 
+/**
+ * @brief   PLLSAIM value.
+ * @note    The allowed values are 2..63.
+ * @note    The default value is calculated for a 96MHz SAI clock
+ *          output from an external 8MHz HSE clock.
+ */
+#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAIM_VALUE         4
+#endif
+
 /**
  * @brief   PLLSAIR value.
  * @note    The allowed values are 2..7.
@@ -851,7 +861,7 @@
  * @note    The allowed values are 2, 4, 6 and 8.
  */
 #if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIP_VALUE         4
+#define STM32_PLLSAIP_VALUE         8
 #endif
 
 /**
@@ -1690,6 +1700,16 @@
 #define STM32_ACTIVATE_PLLSAI       FALSE
 #endif
 
+/**
+ * @brief   STM32_PLLSAIM field.
+ */
+#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) ||        \
+    defined(__DOXYGEN__)
+#define STM32_PLLSAIM               (STM32_PLLSAIM_VALUE << 0)
+#else
+#error "invalid STM32_PLLSAIM_VALUE value specified"
+#endif
+
 /**
  * @brief   STM32_PLLSAIN field.
  */
@@ -1917,7 +1937,7 @@
 #if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
 #define STM32_PLL48CLK              (STM32_PLLVCO / STM32_PLLQ_VALUE)
 #elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI
-#define STM32_PLL48CLK              (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
+#define STM32_PLL48CLK              (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
 #else
 #error "invalid source selected for PLL48CLK clock"
 #endif
-- 
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