From 354bd66eb083691cab4c2c29b32a836805ac5edc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 16 Nov 2010 18:39:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2371 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/hal_lld.h | 65 ++++++++++++--------------- os/hal/platforms/STM8/hal_lld.c | 54 +++++++++++++++-------- os/hal/platforms/STM8/hal_lld.h | 95 +++++++++++++++++++++++++++++++++++----- os/hal/platforms/STM8L/hal_lld.c | 2 +- os/hal/platforms/STM8L/hal_lld.h | 18 ++++++-- 5 files changed, 161 insertions(+), 73 deletions(-) (limited to 'os/hal') diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index e8f71a01f..9cca9401f 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -26,16 +26,13 @@ * - STM32_HSECLK. * . * One of the following macros must also be defined: - * - STM32F100x4, STM32F100x6 for Value Line Low Density devices. - * - STM32F100x8, STM32F100xB for Value Line Medium Density devices. - * - STM32F103x4, STM32F103x6 for Performance Low Density devices. - * - STM32F103x8, STM32F103xB for Performance Medium Density devices. - * - STM32F103xC, STM32F103xD, STM32F103xE, STM32F103xG for - * Performance High Density devices. - * - STM32F105x8, STM32F105xB, STM32F105xC for Connectivity Line - * devices. - * - STM32F107xB, STM32F107xC for Connectivity Line devices with - * Ethernet. + * - STM32F10X_LD_VL for Value Line Low Density devices. + * - STM32F10X_MD_VL for Value Line Medium Density devices. + * - STM32F10X_LD for Performance Low Density devices. + * - STM32F10X_MD for Performance Medium Density devices. + * - STM32F10X_HD for Performance High Density devices. + * - STM32F10X_XD for Performance eXtra Density devices. + * - STM32F10X_CL for Connectivity Line devices. * . * * @addtogroup HAL @@ -63,11 +60,10 @@ #if defined(__DOXYGEN__) #define PLATFORM_NAME "STM32" -#elif defined(STM32F100x4) || defined(STM32F100x6) +#elif defined(STM32F10X_LD_VL) /* * Capability flags for Value Line Low Density devices. */ -#define STM32F10X_LD_VL #define PLATFORM_NAME "STM32 Value Line Low Density" #include "hal_lld_f100.h" @@ -131,11 +127,10 @@ #define STM32_HAS_USB FALSE #define STM32_HAS_USBOTG FALSE -#elif defined(STM32F100x8) || defined(STM32F100xB) +#elif defined(STM32F10X_MD_VL) /* * Capability flags for Value Line Medium Density devices. */ -#define STM32F10X_MD_VL #define PLATFORM_NAME "STM32 Value Line Medium Density" #include "hal_lld_f100.h" @@ -199,11 +194,10 @@ #define STM32_HAS_USB FALSE #define STM32_HAS_USBOTG FALSE -#elif defined(STM32F103x4) || defined(STM32F103x6) +#elif defined(STM32F10X_LD) /* * Capability flags for Performance Line Low Density devices. */ -#define STM32F10X_LD #define PLATFORM_NAME "STM32 Performance Line Low Density" #include "hal_lld_f103.h" @@ -267,11 +261,10 @@ #define STM32_HAS_USB FALSE #define STM32_HAS_USBOTG FALSE -#elif defined(STM32F103x8) || defined(STM32F103xB) +#elif defined(STM32F10X_MD) /* * Capability flags for Performance Line Medium Density devices. */ -#define STM32F10X_MD #define PLATFORM_NAME "STM32 Performance Line Medium Density" #include "hal_lld_f103.h" @@ -335,12 +328,10 @@ #define STM32_HAS_USB TRUE #define STM32_HAS_USBOTG FALSE -#elif defined(STM32F103xC) || defined(STM32F103xD) || \ - defined(STM32F103xE) || defined(STM32F103xG) +#elif defined(STM32F10X_HD) /* * Capability flags for Performance Line High Density devices. */ -#define STM32F10X_HD #define PLATFORM_NAME "STM32 Performance Line High Density" #include "hal_lld_f103.h" @@ -404,20 +395,19 @@ #define STM32_HAS_USB TRUE #define STM32_HAS_USBOTG FALSE -#elif defined(STM32F105x8) || defined(STM32F105xB) || defined(STM32F105xC) +#elif defined(STM32F10X_XD) /* - * Capability flags for Connectivity Line devices. + * Capability flags for Performance Line eXtra Density devices. */ -#define STM32F10X_CL -#define PLATFORM_NAME "STM32 Connectivity Line" -#include "hal_lld_f105_f107.h" +#define PLATFORM_NAME "STM32 Performance Line eXtra Density" +#include "hal_lld_f103.h" #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC3 TRUE #define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE +#define STM32_HAS_CAN2 FALSE #define STM32_HAS_DAC TRUE @@ -431,15 +421,15 @@ #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE #define STM32_HAS_I2C1 TRUE #define STM32_HAS_I2C2 TRUE #define STM32_HAS_RTC TRUE -#define STM32_HAS_SDIO FALSE +#define STM32_HAS_SDIO TRUE #define STM32_HAS_SPI1 TRUE #define STM32_HAS_SPI2 TRUE @@ -452,7 +442,7 @@ #define STM32_HAS_TIM5 TRUE #define STM32_HAS_TIM6 TRUE #define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM8 TRUE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE #define STM32_HAS_TIM11 FALSE @@ -469,15 +459,14 @@ #define STM32_HAS_UART3 TRUE #define STM32_HAS_UART4 TRUE -#define STM32_HAS_USB FALSE -#define STM32_HAS_USBOTG TRUE +#define STM32_HAS_USB TRUE +#define STM32_HAS_USBOTG FALSE -#elif defined(STM32F107xB) || defined(STM32F107xC) +#elif defined(STM32F10X_CL) /* - * Capability flags for Connectivity Line devices with Ethernet. + * Capability flags for Connectivity Line devices. */ -#define STM32F10X_CL -#define PLATFORM_NAME "STM32 Connectivity Line with Ethernet" +#define PLATFORM_NAME "STM32 Connectivity Line" #include "hal_lld_f105_f107.h" #define STM32_HAS_ADC1 TRUE diff --git a/os/hal/platforms/STM8/hal_lld.c b/os/hal/platforms/STM8/hal_lld.c index 0cb3f5e25..de685aa30 100644 --- a/os/hal/platforms/STM8/hal_lld.c +++ b/os/hal/platforms/STM8/hal_lld.c @@ -50,36 +50,47 @@ /** * @brief Low level HAL driver initialization. + * @details Clock sources initialization, HSI is assumed to be already + * started after reset. + * @note If the @p STM8_CLOCK_INIT option is set to @p FALSE then the + * initialization is not performed and is left to the application. * * @notapi */ void hal_lld_init(void) { -#if STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT -#if STM8_CLOCK_SOURCE == CLK_SOURCE_HSI - CLK->ICKR = 1; /* HSIEN */ - while ((CLK->ICKR & 2) == 0) /* HSIRDY */ +#if !STM8_NO_CLOCK_INIT + /* Makes sure that HSI is stable before proceeding.*/ + CLK->ICKR |= CLK_ICKR_HSIRDY; + while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0) ; -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI - CLK->ICKR = 8; /* LSIEN */ - while ((CLK->ICKR & 16) == 0) /* LSIRDY */ - ; -#else /* STM8_CLOCK_SOURCE == CLK_SOURCE_HSE */ - CLK->ECKR = 1; /* HSEEN */ - while ((CLK->ECKR & 2) == 0) /* HSERDY */ + + /* LSI startup and stabilization if required.*/ +#if STM8_LSI_ENABLED + CLK->ICKR |= CLK_ICKR_LSIEN; + while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0) ; #endif -#if STM8_CLOCK_SOURCE != CLK_SOURCE_HSI - /* Switching clock (manual switch mode).*/ - CLK->SWCR = 0; - CLK->SWR = STM8_CLOCK_SOURCE; - while ((CLK->SWCR & 8) == 0) /* SWIF */ + + /* HSE startup and stabilization if required.*/ +#if STM8_HSE_ENABLED + CLK->ECKR |= CLK_ECKCR_HSEEN; + while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0) ; - CLK->SWCR = 2; /* SWEN */ #endif + /* Setting up clock dividers.*/ CLK->CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0); + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + /* Clocks initially all disabled.*/ CLK->PCKENR1 = 0; CLK->PCKENR2 = 0; @@ -87,8 +98,13 @@ void hal_lld_init(void) { /* Other clock related initializations.*/ CLK->CSSR = 0; CLK->CCOR = 0; - CLK->CANCCR = 0; -#endif /* STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT */ + CLK->CANCCR = STM8_CAN_DIVIDER_VALUE; + + /* HSI disabled if it is no more required.*/ +#if !STM8_HSI_ENABLED + CLK->ICKR &= ~CLK_ICKR_HSION; +#endif +#endif /* !STM8_NO_CLOCK_INIT */ } /** @} */ diff --git a/os/hal/platforms/STM8/hal_lld.h b/os/hal/platforms/STM8/hal_lld.h index a7bcbe89a..6e2c585d2 100644 --- a/os/hal/platforms/STM8/hal_lld.h +++ b/os/hal/platforms/STM8/hal_lld.h @@ -20,6 +20,17 @@ /** * @file STM8/hal_lld.h * @brief STM8 HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * . + * One of the following macros must also be defined: + * - STM8S103. + * - STM8S105. + * - STM8S207. + * - STM8S208. + * - STM8S903. + * . * * @addtogroup HAL * @{ @@ -37,15 +48,14 @@ /** * @brief Platform name. */ -#define PLATFORM_NAME "STM8x" +#define PLATFORM_NAME "STM8S" #define LSICLK 128000 /**< Low speed internal clock. */ #define HSICLK 16000000 /**< High speed internal clock. */ -#define CLK_SOURCE_DEFAULT 0 /**< No clock initialization. */ -#define CLK_SOURCE_HSI 0xE1 /**< HSI clock selector. */ -#define CLK_SOURCE_LSI 0xD2 /**< LSI clock selector. */ -#define CLK_SOURCE_HSE 0xB4 /**< HSE clock selector. */ +#define CLK_SYSSEL_HSI 0xE1 /**< HSI clock selector. */ +#define CLK_SYSSEL_LSI 0xD2 /**< LSI clock selector. */ +#define CLK_SYSSEL_HSE 0xB4 /**< HSE clock selector. */ #define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */ #define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */ @@ -65,11 +75,39 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8_HSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8_HSE_ENABLED TRUE +#endif + /** * @brief Clock source setting. */ -#if !defined(STM8_CLOCK_SOURCE) || defined(__DOXYGEN__) -#define STM8_CLOCK_SOURCE CLK_SOURCE_DEFAULT +#if !defined(STM8_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSE #endif /** @@ -86,6 +124,13 @@ #define STM8_CPU_DIVIDER CLK_CPU_DIV1 #endif +/** + * @brief bxCAN divider value. + */ +#if !defined(STM8_CAN_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define STM8_CAN_DIVIDER_VALUE 1 +#endif + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -108,18 +153,46 @@ #error "specified invalid CPU divider" #endif -#if STM8_CLOCK_SOURCE == CLK_SOURCE_DEFAULT +#if (STM8_CAN_DIVIDER_VALUE < 1) || (STM8_CAN_DIVIDER_VALUE > 8) +#error "specified invalid CAN divider value" +#endif + +#if STM8_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if !STM8_HSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8_LSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8_HSE_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE) +#error "requested HSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) #define SYSCLK (HSICLK / 8) -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSI +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI #define SYSCLK (HSICLK / (1 << STM8_HSI_DIVIDER)) -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI #define SYSCLK LSICLK -#elif STM8_CLOCK_SOURCE == CLK_SOURCE_HSE +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE #define SYSCLK HSECLK #else #error "specified invalid clock source" #endif +/** + * @brief CPU clock. + * @details On the STM8S the CPU clock can be programmed to be a fraction of + * the system clock. + */ #define CPUCLK (SYSCLK / (1 << STM8_CPU_DIVIDER)) /*===========================================================================*/ diff --git a/os/hal/platforms/STM8L/hal_lld.c b/os/hal/platforms/STM8L/hal_lld.c index 2d5014303..72cb830f3 100644 --- a/os/hal/platforms/STM8L/hal_lld.c +++ b/os/hal/platforms/STM8L/hal_lld.c @@ -100,7 +100,7 @@ void hal_lld_init(void) { /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ #if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI /* Switching clock (manual switch mode).*/ - CLK->SWR = STM8_CLOCK_SOURCE; + CLK->SWR = STM8L_SYSCLK_SOURCE; while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) ; CLK->SWCR = CLK_SWCR_SWEN; diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h index 1df041782..2e21988e7 100644 --- a/os/hal/platforms/STM8L/hal_lld.h +++ b/os/hal/platforms/STM8L/hal_lld.h @@ -42,9 +42,7 @@ #undef FALSE #undef TRUE - #include "stm8l15x.h" - #define FALSE 0 #define TRUE (!FALSE) @@ -217,7 +215,10 @@ #error "requested LSE clock is not enabled" #endif -#if STM8L_NO_CLOCK_INIT +/** + * @brief System clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) #define SYSCLK (HSICLK / 8) #elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI #define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER)) @@ -231,7 +232,10 @@ #error "specified invalid SYSCLK source" #endif -#if STM8L_NO_CLOCK_INIT +/** + * @brief RTC clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) #define RTCCLK 0 #elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI #define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER)) @@ -245,6 +249,12 @@ #error "specified invalid RTCCLK source" #endif +/** + * @brief CPU clock. + * @details On the STM8L the CPU clock is always equal to the system clock. + */ +#define CPUCLK SYSCLK + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3