From 1f10e52dd5cc8f8539757e61e630265b92a4cd95 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 23 Oct 2015 18:44:40 +0000 Subject: Fixed bug #651. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8385 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/stm32_isr.h | 12 +++ os/hal/ports/STM32/STM32F0xx/stm32_rcc.h | 162 +++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+) (limited to 'os/hal') diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h index 7cd057f8c..fd8c24918 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h @@ -55,11 +55,23 @@ #define STM32_TIM1_CC_HANDLER Vector78 #define STM32_TIM2_HANDLER Vector7C #define STM32_TIM3_HANDLER Vector80 +#define STM32_TIM6_HANDLER Vector84 +#define STM32_TIM7_HANDLER Vector88 +#define STM32_TIM14_HANDLER Vector8C +#define STM32_TIM15_HANDLER Vector90 +#define STM32_TIM16_HANDLER Vector94 +#define STM32_TIM17_HANDLER Vector98 #define STM32_TIM1_UP_NUMBER 13 #define STM32_TIM1_CC_NUMBER 14 #define STM32_TIM2_NUMBER 15 #define STM32_TIM3_NUMBER 16 +#define STM32_TIM6_NUMBER 17 +#define STM32_TIM7_NUMBER 18 +#define STM32_TIM14_NUMBER 19 +#define STM32_TIM15_NUMBER 20 +#define STM32_TIM16_NUMBER 21 +#define STM32_TIM17_NUMBER 22 /* * USART units. diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h index 8fc8e933e..22b0e8806 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h @@ -555,6 +555,168 @@ * @api */ #define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) + +/** + * @brief Enables the TIM7 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPB1(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM15(lp) rccDisableAPB1(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPB1(RCC_APB2RSTR_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB1(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM16(lp) rccDisableAPB1(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB1(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB1(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM17(lp) rccDisableAPB1(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB1(RCC_APB2RSTR_TIM17RST) /** @} */ /** -- cgit v1.2.3