From 1eabe1e91173d56ccbd85092570b3d0bfb8346e9 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Mon, 6 Mar 2017 14:26:19 +0000
Subject: Fixed support for QUADSPI on F4xx.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10120 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32F4xx/stm32_rcc.h      | 30 +++++++++++++++++++++++++++
 os/hal/ports/STM32/STM32F4xx/stm32_registry.h |  4 ++--
 2 files changed, 32 insertions(+), 2 deletions(-)

(limited to 'os/hal')

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index 6f3e269e6..503cf1bae 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -713,6 +713,36 @@
 #define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
 /** @} */
 
+/**
+ * @name    QUADSPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief   Disables the QUADSPI1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
+
+/**
+ * @brief   Resets the QUADSPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
+/** @} */
+
 /**
  * @name    SDIO peripheral specific RCC operations
  * @{
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index 941deffd7..ef21d7136 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -595,8 +595,8 @@
 
 /* QUADSPI attributes.*/
 #define STM32_HAS_QUADSPI1                  TRUE
-#define STM32_QUADSPI1_HANDLER              Vector1AC
-#define STM32_QUADSPI1_NUMBER               91
+#define STM32_QUADSPI1_HANDLER              Vector1B0
+#define STM32_QUADSPI1_NUMBER               92
 #define STM32_QUADSPI1_DMA_MSK              STM32_DMA_STREAM_ID_MSK(2, 7)
 #define STM32_QUADSPI1_DMA_CHN              0x30000000
 
-- 
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