From 1abe0779f51d974ac3c9dcb9a552f0b5095f40dc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 20 Dec 2018 17:47:55 +0000 Subject: experiment git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12481 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk | 2 + os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt | 26 ++ os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c | 587 +++++++++++++++++++++++++++ os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h | 399 ++++++++++++++++++ 4 files changed, 1014 insertions(+) create mode 100644 os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk create mode 100644 os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt create mode 100644 os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c create mode 100644 os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h (limited to 'os/hal') diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk b/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk new file mode 100644 index 000000000..6080cec58 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMAv1_MUX/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt b/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt new file mode 100644 index 000000000..dc4663890 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMAv1_MUX/notes.txt @@ -0,0 +1,26 @@ +STM32 DMAv1 driver. + +Driver capability: + +- The driver supports the STM32 traditional DMA controller in the following + configurations: 5ch, 7ch, 7ch+5ch, 7ch+7ch. +- Support for automatic the channel selection through the CSELR register. +- For devices without CSELR register it is possible to select channels but + the SYSCFG CFGR register is not configured, the user has to configure it + before starting the DMA driver. +- The driver supports shared ISR handlers with a quirk: the IRQ priority is + established by the first allocated channel among the channels sharing the + ISR. + +The file registry must export: + +STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other + drivers use it to enable checks on DMA + channels. Probably will be removed in the + future. +STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register. +STM32_DMA_SUPPORTS_DMAMUX - TRUE if the DMA is riven by a DMAMUX. +STM32_DMAn_NUM_CHANNELS - Number of channels in DMAs "n" (1..2). +STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x" (1..7). If the macro + is not exported then the ISR is not declared. +STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x" (1..7). diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c new file mode 100644 index 000000000..c1e0d623c --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.c @@ -0,0 +1,587 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1_MUX/stm32_dma.c + * @brief DMA helper driver code. + * + * @addtogroup STM32_DMA + * @details DMA sharing helper driver. In the STM32 the DMA streams are a + * shared resource, this driver allows to allocate and free DMA + * streams at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * ISRs when allocating streams. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Mask of the DMA1 streams in @p dma_streams_mask. + */ +#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U) + +/** + * @brief Mask of the DMA2 streams in @p dma_streams_mask. + */ +#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - 1U) << 8U) + +/** + * @brief Mask of all DMA streams. + */ +#define STM32_DMA_STREAMS_MASK (STM32_DMA1_STREAMS_MASK | STM32_DMA2_STREAMS_MASK) + +/** + * @brief Post-reset value of the stream CCR register. + */ +#define STM32_DMA_CCR_RESET_VALUE 0x00000000U + +/* + * Default ISR collision masks. + */ +#if !defined(DMA1_CH1_CMASK) +#define DMA1_CH1_CMASK 0x00000001U +#endif + +#if !defined(DMA1_CH2_CMASK) +#define DMA1_CH2_CMASK 0x00000002U +#endif + +#if !defined(DMA1_CH3_CMASK) +#define DMA1_CH3_CMASK 0x00000004U +#endif + +#if !defined(DMA1_CH4_CMASK) +#define DMA1_CH4_CMASK 0x00000008U +#endif + +#if !defined(DMA1_CH5_CMASK) +#define DMA1_CH5_CMASK 0x00000010U +#endif + +#if !defined(DMA1_CH6_CMASK) +#define DMA1_CH6_CMASK 0x00000020U +#endif + +#if !defined(DMA1_CH7_CMASK) +#define DMA1_CH7_CMASK 0x00000040U +#endif + +#if !defined(DMA2_CH1_CMASK) +#define DMA2_CH1_CMASK 0x00000080U +#endif + +#if !defined(DMA2_CH2_CMASK) +#define DMA2_CH2_CMASK 0x00000100U +#endif + +#if !defined(DMA2_CH3_CMASK) +#define DMA2_CH3_CMASK 0x00000200U +#endif + +#if !defined(DMA2_CH4_CMASK) +#define DMA2_CH4_CMASK 0x00000400U +#endif + +#if !defined(DMA2_CH5_CMASK) +#define DMA2_CH5_CMASK 0x00000800U +#endif + +#if !defined(DMA2_CH6_CMASK) +#define DMA2_CH6_CMASK 0x00001000U +#endif + +#if !defined(DMA2_CH7_CMASK) +#define DMA2_CH7_CMASK 0x00002000U +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief DMA streams descriptors. + * @details This table keeps the association between an unique stream + * identifier and the involved physical registers. + * @note Don't use this array directly, use the appropriate wrapper macros + * instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc. + */ +const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { + {DMA1, DMA1_Channel1, DMA1_CH1_CMASK, DMAMUX1_Channel0, 0, 0, STM32_DMA1_CH1_NUMBER}, + {DMA1, DMA1_Channel2, DMA1_CH2_CMASK, DMAMUX1_Channel1, 4, 1, STM32_DMA1_CH2_NUMBER}, + {DMA1, DMA1_Channel3, DMA1_CH3_CMASK, DMAMUX1_Channel2, 8, 2, STM32_DMA1_CH3_NUMBER}, + {DMA1, DMA1_Channel4, DMA1_CH4_CMASK, DMAMUX1_Channel3, 12, 3, STM32_DMA1_CH4_NUMBER}, + {DMA1, DMA1_Channel5, DMA1_CH5_CMASK, DMAMUX1_Channel4, 16, 4, STM32_DMA1_CH5_NUMBER}, +#if STM32_DMA1_NUM_CHANNELS > 5 + {DMA1, DMA1_Channel6, DMA1_CH6_CMASK, DMAMUX1_Channel5, 20, 5, STM32_DMA1_CH6_NUMBER}, +#endif +#if STM32_DMA1_NUM_CHANNELS > 6 + {DMA1, DMA1_Channel7, DMA1_CH7_CMASK, DMAMUX1_Channel6, 24, 6, STM32_DMA1_CH7_NUMBER}, +#endif +#if STM32_DMA2_NUM_CHANNELS > 0 + {DMA2, DMA2_Channel1, DMA2_CH1_CMASK, DMAMUX1_Channel7, 0, 7, STM32_DMA2_CH1_NUMBER}, + {DMA2, DMA2_Channel2, DMA2_CH2_CMASK, DMAMUX1_Channel8, 4, 8, STM32_DMA2_CH2_NUMBER}, + {DMA2, DMA2_Channel3, DMA2_CH3_CMASK, DMAMUX1_Channel9, 8, 9, STM32_DMA2_CH3_NUMBER}, + {DMA2, DMA2_Channel4, DMA2_CH4_CMASK, DMAMUX1_Channel10, 12, 10, STM32_DMA2_CH4_NUMBER}, + {DMA2, DMA2_Channel5, DMA2_CH5_CMASK, DMAMUX1_Channel11, 16, 11, STM32_DMA2_CH5_NUMBER}, +#endif +#if STM32_DMA2_NUM_CHANNELS > 5 + {DMA2, DMA2_Channel6, DMA2_CH6_CMASK, DMAMUX1_Channel12, 20, 12, STM32_DMA2_CH6_NUMBER}, +#endif +#if STM32_DMA2_NUM_CHANNELS > 6 + {DMA2, DMA2_Channel7, DMA2_CH7_CMASK, DMAMUX1_Channel13, 24, 13, STM32_DMA2_CH7_NUMBER}, +#endif +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Global DMA-related data structures. + */ +static struct { + /** + * @brief Mask of the allocated streams. + */ + uint32_t allocated_mask; + /** + * @brief Mask of the enabled streams ISRs. + */ + uint32_t isr_mask; + /** + * @brief DMA IRQ redirectors. + */ + struct { + /** + * @brief DMA callback function. + */ + stm32_dmaisr_t func; + /** + * @brief DMA callback parameter. + */ + void *param; + } streams[STM32_DMA_STREAMS]; +} dma; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if defined(STM32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 1 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 2 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 3 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 4 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 5 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 6 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 stream 7 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA1_STREAM7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 1 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 2 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 3 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 4 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 5 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 6 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if defined(STM32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA2 stream 7 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + dmaServeInterrupt(STM32_DMA2_STREAM7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dma.streams_mask = 0U; + dma.isr_mask = 0U; + for (i = 0; i < STM32_DMA_STREAMS; i++) { + _stm32_dma_streams[i].channel->CCR = STM32_DMA_CCR_RESET_VALUE; + } + DMA1->IFCR = 0xFFFFFFFFU; +#if STM32_DMA2_NUM_CHANNELS > 0 + DMA2->IFCR = 0xFFFFFFFFU; +#endif +} + +/** + * @brief Allocates a DMA stream. + * @details The stream is allocated and, if required, the DMA clock enabled. + * The function also enables the IRQ vector associated to the stream + * and initializes its priority. + * @pre The stream must not be already in use or an error is returned. + * @post The stream is allocated and the default ISR handler redirected + * to the specified function. + * @post The stream ISR vector is enabled and its priority configured. + * @post The stream must be freed using @p dmaStreamRelease() before it can + * be reused with another peripheral. + * @post The stream is in its post-reset state. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] priority IRQ priority for the DMA stream + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The allocated @p stm32_dma_stream_t object. + * @retval NULL no stream available. + * + * @special + */ +const stm32_dma_stream_t *dmaStreamAllocate(uint32_t priority, + stm32_dmaisr_t func, + void *param) { + + /* Checks if the stream is already taken.*/ + if ((dma.streams_mask & (1U << dmastp->selfindex)) != 0U) + return true; + + /* Installs the DMA handler.*/ + _stm32_dma_isr_redir[dmastp->selfindex].dma_func = func; + _stm32_dma_isr_redir[dmastp->selfindex].dma_param = param; + + /* Enabling DMA clocks required by the current streams set.*/ + if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { + rccEnableDMA1(true); + } +#if STM32_DMA2_NUM_CHANNELS > 0 + if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { + rccEnableDMA2(true); + } +#endif + +#if STM32_DMA_SUPPORTS_DMAMUX == TRUE + /* Enabling DMAMUX if present.*/ + if (dma.streams_mask == 0U) { + rccEnableDMAMUX(true); + } +#endif + + /* Putting the stream in a safe state.*/ + dmaStreamDisable(dmastp); + dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + + /* Enables the associated IRQ vector if not already enabled and if a + callback is defined.*/ + if (func != NULL) { + if ((dma.isr_mask & dmastp->cmask) == 0U) { + nvicEnableVector(dmastp->vector, priority); + } + dma.isr_mask |= (1U << dmastp->selfindex); + } + + /* Marks the stream as allocated.*/ + dma.streams_mask |= (1U << dmastp->selfindex); + + return false; +} + +/** + * @brief Releases a DMA stream. + * @details The stream is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated stream is an illegal operation + * and is trapped if assertions are enabled. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post The stream is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { + + osalDbgCheck(dmastp != NULL); + + /* Check if the streams is not taken.*/ + osalDbgAssert((dma.streams_mask & (1 << dmastp->selfindex)) != 0U, + "not allocated"); + + /* Marks the stream as not allocated.*/ + dma.streams_mask &= ~(1U << dmastp->selfindex); + dma.isr_mask &= ~(1U << dmastp->selfindex); + + /* Disables the associated IRQ vector if it is no more in use.*/ + if ((dma.streams_mask & dmastp->cmask) == 0U) { + nvicDisableVector(dmastp->vector); + } + + /* Removes the DMA handler.*/ + _stm32_dma_isr_redir[dmastp->selfindex].dma_func = NULL; + _stm32_dma_isr_redir[dmastp->selfindex].dma_param = NULL; + + /* Shutting down clocks that are no more required, if any.*/ + if ((dma.streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) { + rccDisableDMA1(); + } +#if STM32_DMA2_NUM_CHANNELS > 0 + if ((dma.streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) { + rccDisableDMA2(); + } +#endif + +#if STM32_DMA_SUPPORTS_DMAMUX == TRUE + /* Shutting down DMAMUX if present.*/ + if (dma.streams_mask == 0U) { + rccDisableDMAMUX(); + } +#endif +} + +#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) +/** + * @brief Associates a peripheral request to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmastp pointer to a @p stm32_dma_stream_t structure + * @param[in] per peripheral identifier + * + * @special + */ +void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per) { + + osalDbgCheck(per < 256U); + + dmastp->mux->CCR = per; +} +#endif + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h new file mode 100644 index 000000000..b7cc3b999 --- /dev/null +++ b/os/hal/ports/STM32/LLD/DMAv1_MUX/stm32_dma.h @@ -0,0 +1,399 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file DMAv1_MUX/stm32_dma.h + * @brief DMA helper driver header. + * @note This driver uses the new naming convention used for the STM32F2xx + * so the "DMA channels" are referred as "DMA streams". + * + * @addtogroup STM32_DMA + * @{ + */ + +#ifndef STM32_DMA_H +#define STM32_DMA_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief DMA capability. + * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, + * scatter gather and other advanced features. + */ +#define STM32_DMA_ADVANCED FALSE + +/** + * @brief Total number of DMA streams. + * @details This is the total number of streams among all the DMA units. + */ +#define STM32_DMA_STREAMS (STM32_DMA1_NUM_CHANNELS + \ + STM32_DMA2_NUM_CHANNELS) + +/** + * @brief Mask of the ISR bits passed to the DMA callback functions. + */ +#define STM32_DMA_ISR_MASK 0x0E + +/** + * @brief From stream number to shift factor in @p ISR and @p IFCR registers. + */ +#define STM32_DMA_ISR_SHIFT(stream) (((stream) - 1U) * 4U) + +/** + * @brief Checks if a DMA priority is within the valid range. + * @param[in] prio DMA priority + * + * @retval The check result. + * @retval false invalid DMA priority. + * @retval true correct DMA priority. + */ +#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U)) + +/** + * @brief Checks if a DMA channel is within the valid range. + * + * @param[in] ch DMA channel + * @retval The check result. + * @retval FALSE invalid DMA channel. + * @retval TRUE correct DMA channel. + */ +#define STM32_DMA_IS_VALID_CHANNEL(ch) (((ch) >= 0U) && ((ch) < STM32_DMA_STREAMS)) + +/** + * @name CR register constants common to all DMA types + * @{ + */ +#define STM32_DMA_CR_EN DMA_CCR_EN +#define STM32_DMA_CR_TEIE DMA_CCR_TEIE +#define STM32_DMA_CR_HTIE DMA_CCR_HTIE +#define STM32_DMA_CR_TCIE DMA_CCR_TCIE +#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM) +#define STM32_DMA_CR_DIR_P2M 0U +#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR +#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM +#define STM32_DMA_CR_CIRC DMA_CCR_CIRC +#define STM32_DMA_CR_PINC DMA_CCR_PINC +#define STM32_DMA_CR_MINC DMA_CCR_MINC +#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE +#define STM32_DMA_CR_PSIZE_BYTE 0U +#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0 +#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1 +#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE +#define STM32_DMA_CR_MSIZE_BYTE 0U +#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0 +#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1 +#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \ + STM32_DMA_CR_MSIZE_MASK) +#define STM32_DMA_CR_PL_MASK DMA_CCR_PL +#define STM32_DMA_CR_PL(n) ((n) << 12U) +/** @} */ + +/** + * @name Request line selector macro + * @{ + */ +#define STM32_DMA_CR_CHSEL_MASK 0U +#define STM32_DMA_CR_CHSEL(n) 0U +/** @} */ + +/** + * @name CR register constants only found in enhanced DMA + * @{ + */ +#define STM32_DMA_CR_DMEIE 0U /**< @brief Ignored by normal DMA. */ +/** @} */ + +/** + * @name Status flags passed to the ISR callbacks + * @{ + */ +#define STM32_DMA_ISR_FEIF 0U +#define STM32_DMA_ISR_DMEIF 0U +#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 +#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 +#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(STM32_DMA_SUPPORTS_DMAMUX) +#error "STM32_DMA_SUPPORTS_DMAMUX not defined in registry" +#endif + +#if STM32_DMA_SUPPORTS_DMAMUX == FALSE +#error "this driver requires a DMAMUX unit" +#else +#include "stm32_dmamux.h" +#endif + +#if !defined(STM32_DMA1_NUM_CHANNELS) +#error "STM32_DMA1_NUM_CHANNELS not defined in registry" +#endif + +#if !defined(STM32_DMA2_NUM_CHANNELS) +#error "STM32_DMA2_NUM_CHANNELS not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a DMA callback. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register, the bits + * are aligned to bit zero + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/** + * @brief Type of a DMA stream descriptor structure. + */ +typedef struct { + DMA_TypeDef *dma ; /**< @brief Associated DMA. */ + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + uint32_t cmask; /**< @brief Mask of streams sharing + the same ISR. */ + DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */ + uint8_t shift; /**< @brief Bit offset in ISR, IFCR + and CSELR registers. */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ +} stm32_dma_stream_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions + * @{ + */ +/** + * @brief Associates a peripheral data register to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CPAR register + * + * @special + */ +#define dmaStreamSetPeripheral(dmastp, addr) { \ + (dmastp)->channel->CPAR = (uint32_t)(addr); \ +} + +/** + * @brief Associates a memory destination to a DMA stream. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] addr value to be written in the CMAR register + * + * @special + */ +#define dmaStreamSetMemory0(dmastp, addr) { \ + (dmastp)->channel->CMAR = (uint32_t)(addr); \ +} + +/** + * @brief Sets the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] size value to be written in the CNDTR register + * + * @special + */ +#define dmaStreamSetTransactionSize(dmastp, size) { \ + (dmastp)->channel->CNDTR = (uint32_t)(size); \ +} + +/** + * @brief Returns the number of transfers to be performed. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @return The number of transfers to be performed. + * + * @special + */ +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR)) + +/** + * @brief Programs the stream mode settings. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register + * + * @special + */ +#define dmaStreamSetMode(dmastp, mode) { \ + (dmastp)->channel->CCR = (uint32_t)(mode); \ +} + +/** + * @brief DMA stream enable. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamEnable(dmastp) { \ + (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ +} + +/** + * @brief DMA stream disable. + * @details The function disables the specified stream and then clears any + * pending interrupt. + * @note This function can be invoked in both ISR or thread context. + * @note Interrupts enabling flags are set to zero after this call, see + * bug 3607518. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ + STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + dmaStreamClearInterrupt(dmastp); \ +} + +/** + * @brief DMA stream interrupt sources clear. + * @note This function can be invoked in both ISR or thread context. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * + * @special + */ +#define dmaStreamClearInterrupt(dmastp) { \ + (dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \ +} + +/** + * @brief Starts a memory to memory operation using the specified stream. + * @note The default transfer data mode is "byte to byte" but it can be + * changed by specifying extra options in the @p mode parameter. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + * @param[in] mode value to be written in the CCR register, this value + * is implicitly ORed with: + * - @p STM32_DMA_CR_MINC + * - @p STM32_DMA_CR_PINC + * - @p STM32_DMA_CR_DIR_M2M + * - @p STM32_DMA_CR_EN + * . + * @param[in] src source address + * @param[in] dst destination address + * @param[in] n number of data units to copy + */ +#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \ + dmaStreamSetPeripheral(dmastp, src); \ + dmaStreamSetMemory0(dmastp, dst); \ + dmaStreamSetTransactionSize(dmastp, n); \ + dmaStreamSetMode(dmastp, (mode) | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ + STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ +} + +/** + * @brief Polled wait for DMA transfer end. + * @pre The stream must have been allocated using @p dmaStreamAllocate(). + * @post After use the stream can be released using @p dmaStreamRelease(). + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaWaitCompletion(dmastp) { \ + while ((dmastp)->channel->CNDTR > 0U) \ + ; \ + dmaStreamDisable(dmastp); \ +} + +/** + * @brief Serves a DMA IRQ. + * + * @param[in] dmastp pointer to a stm32_dma_stream_t structure + */ +#define dmaServeInterrupt(dmastp) { \ + uint32_t flags; \ + uint32_t idx = (dmastp)->selfindex; \ + \ + flags = ((dmastp)->dma->ISR >> (dmastp)->shift) & STM32_DMA_ISR_MASK; \ + if (flags & (dmastp)->channel->CCR) { \ + (dmastp)->dma->IFCR = flags << (dmastp)->shift; \ + if (_stm32_dma_isr_redir[idx].dma_func) { \ + _stm32_dma_isr_redir[idx].dma_func(_stm32_dma_isr_redir[idx].dma_param, flags); \ + } \ + } \ +} +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + const stm32_dma_stream_t *dmaStreamAllocate(uint32_t priority, + stm32_dmaisr_t func, + void *param); + void dmaStreamRelease(const stm32_dma_stream_t *dmastp); + void dmaSetRequestSource(const stm32_dma_stream_t *dmastp, uint32_t per); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_DMA_H */ + +/** @} */ -- cgit v1.2.3