From fbc0d4b082178ac1018586f0efa0f3f4160355f8 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 8 Jan 2018 09:12:47 +0000 Subject: Unified MPU handler. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11234 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h | 2 - os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 2 - os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h | 1 - os/hal/ports/STM32/STM32F0xx/hal_lld.h | 1 + os/hal/ports/STM32/STM32F1xx/hal_lld.h | 2 + os/hal/ports/STM32/STM32F37x/hal_lld.h | 2 + os/hal/ports/STM32/STM32F3xx/hal_lld.h | 2 + os/hal/ports/STM32/STM32F4xx/hal_lld.h | 2 + os/hal/ports/STM32/STM32F7xx/hal_lld.h | 3 +- os/hal/ports/STM32/STM32H7xx/hal_lld.h | 3 +- os/hal/ports/STM32/STM32L0xx/hal_lld.h | 1 + os/hal/ports/STM32/STM32L1xx/hal_lld.h | 2 + os/hal/ports/STM32/STM32L4xx/hal_lld.h | 2 + os/hal/ports/common/ARMCMx/mpu_v7m.h | 214 +++++++++++++++++++++++++++++++ 14 files changed, 232 insertions(+), 7 deletions(-) create mode 100644 os/hal/ports/common/ARMCMx/mpu_v7m.h (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h index ffa438003..6dfd6debf 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.h @@ -27,8 +27,6 @@ #ifndef STM32_DMA_H #define STM32_DMA_H -#include "cache.h" - /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index 112af2e80..e725a2e5d 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -25,8 +25,6 @@ #ifndef STM32_DMA_H #define STM32_DMA_H -#include "cache.h" - /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h index f6208f9e8..67f22247b 100644 --- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h @@ -25,7 +25,6 @@ #ifndef STM32_DMA_H #define STM32_DMA_H -#include "cache.h" #include "stm32_dmamux.h" /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index aebd833c9..ec20a2c34 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -972,6 +972,7 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld.h b/os/hal/ports/STM32/STM32F1xx/hal_lld.h index 32a63c875..27b829b52 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld.h @@ -205,6 +205,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.h b/os/hal/ports/STM32/STM32F37x/hal_lld.h index aeb4a1ed4..f7db70cdc 100644 --- a/os/hal/ports/STM32/STM32F37x/hal_lld.h +++ b/os/hal/ports/STM32/STM32F37x/hal_lld.h @@ -983,6 +983,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_registry.h" #include "stm32_isr.h" #include "stm32_dma.h" diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index ec6a78eb1..1232ec395 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -1144,6 +1144,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index e9ce800b4..12356cbf3 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -1990,6 +1990,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 66142d435..d84e2333f 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -2037,7 +2037,8 @@ /* Various helpers.*/ #include "nvic.h" -#include "mpu.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 78cc6b7fc..7217a579f 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -2874,7 +2874,8 @@ /* Various helpers.*/ #include "nvic.h" -#include "mpu.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_bdma.h" diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index 46b104218..6811ef313 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -1188,6 +1188,7 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h index f4d47278d..7c7dfce0b 100644 --- a/os/hal/ports/STM32/STM32L1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h @@ -841,6 +841,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 35a05e743..14232e090 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -2175,6 +2175,8 @@ /* Various helpers.*/ #include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/common/ARMCMx/mpu_v7m.h b/os/hal/ports/common/ARMCMx/mpu_v7m.h new file mode 100644 index 000000000..d8521d5f3 --- /dev/null +++ b/os/hal/ports/common/ARMCMx/mpu_v7m.h @@ -0,0 +1,214 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file common/ARMCMx/mpu_v7m.h + * @brief ARMv7-M MPU support macros and structures. + * + * @addtogroup COMMON_ARMCMx_MPUv7M + * @{ + */ + +#ifndef MPUV7M_H +#define MPUV7M_H + +/* Other layers may include another header named mpu.h which is perfectly + compatible, doing a check here to avoid name conflicts.*/ +#ifndef MPU_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name MPU registers definitions + * @{ + */ +#define MPU_TYPE_SEPARATED (1U << 0U) +#define MPU_TYPE_DREGION(n) (((n) >> 8U) & 255U) +#define MPU_TYPE_IREGION(n) (((n) >> 16U) & 255U) + +#define MPU_CTRL_ENABLE (1U << 0U) +#define MPU_CTRL_HFNMIENA (1U << 1U) +#define MPU_CTRL_PRIVDEFENA (1U << 2U) + +#define MPU_RNR_REGION_MASK (255U << 0U) +#define MPU_RNR_REGION(n) ((n) << 0U) + +#define MPU_RBAR_REGION_MASK (15U << 0U) +#define MPU_RBAR_REGION(n) ((n) << 0U) +#define MPU_RBAR_VALID (1U << 4U) +#define MPU_RBAR_ADDR_MASK 0xFFFFFFE0U +#define MPU_RBAR_ADDR(n) ((n) << 5U) + +#define MPU_RASR_ENABLE (1U << 0U) +#define MPU_RASR_SIZE_MASK (31U << 1U) +#define MPU_RASR_SIZE(n) ((n) << 1U) +#define MPU_RASR_SIZE_32 MPU_RASR_SIZE(4U) +#define MPU_RASR_SIZE_64 MPU_RASR_SIZE(5U) +#define MPU_RASR_SIZE_128 MPU_RASR_SIZE(6U) +#define MPU_RASR_SIZE_256 MPU_RASR_SIZE(7U) +#define MPU_RASR_SIZE_512 MPU_RASR_SIZE(8U) +#define MPU_RASR_SIZE_1K MPU_RASR_SIZE(9U) +#define MPU_RASR_SIZE_2K MPU_RASR_SIZE(10U) +#define MPU_RASR_SIZE_4K MPU_RASR_SIZE(11U) +#define MPU_RASR_SIZE_8K MPU_RASR_SIZE(12U) +#define MPU_RASR_SIZE_16K MPU_RASR_SIZE(13U) +#define MPU_RASR_SIZE_32K MPU_RASR_SIZE(14U) +#define MPU_RASR_SIZE_64K MPU_RASR_SIZE(15U) +#define MPU_RASR_SIZE_128K MPU_RASR_SIZE(16U) +#define MPU_RASR_SIZE_256K MPU_RASR_SIZE(17U) +#define MPU_RASR_SIZE_512K MPU_RASR_SIZE(18U) +#define MPU_RASR_SIZE_1M MPU_RASR_SIZE(19U) +#define MPU_RASR_SIZE_2M MPU_RASR_SIZE(20U) +#define MPU_RASR_SIZE_4M MPU_RASR_SIZE(21U) +#define MPU_RASR_SIZE_8M MPU_RASR_SIZE(22U) +#define MPU_RASR_SIZE_16M MPU_RASR_SIZE(23U) +#define MPU_RASR_SIZE_32M MPU_RASR_SIZE(24U) +#define MPU_RASR_SIZE_64M MPU_RASR_SIZE(25U) +#define MPU_RASR_SIZE_128M MPU_RASR_SIZE(26U) +#define MPU_RASR_SIZE_256M MPU_RASR_SIZE(27U) +#define MPU_RASR_SIZE_512M MPU_RASR_SIZE(28U) +#define MPU_RASR_SIZE_1G MPU_RASR_SIZE(29U) +#define MPU_RASR_SIZE_2G MPU_RASR_SIZE(30U) +#define MPU_RASR_SIZE_4G MPU_RASR_SIZE(31U) +#define MPU_RASR_SRD_MASK (255U << 8U) +#define MPU_RASR_SRD(n) ((n) << 8U) +#define MPU_RASR_SRD_ALL (0U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB0 (1U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB1 (2U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB2 (4U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB3 (8U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB4 (16U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB5 (32U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB6 (64U << 8U) +#define MPU_RASR_SRD_DISABLE_SUB7 (128U << 8U) +#define MPU_RASR_ATTR_B (1U << 16U) +#define MPU_RASR_ATTR_C (1U << 17U) +#define MPU_RASR_ATTR_S (1U << 18U) +#define MPU_RASR_ATTR_TEX_MASK (7U << 19U) +#define MPU_RASR_ATTR_TEX(n) ((n) << 19U) +#define MPU_RASR_ATTR_AP_MASK (7U << 24U) +#define MPU_RASR_ATTR_AP(n) ((n) << 24U) +#define MPU_RASR_ATTR_AP_NA_NA (0U << 24U) +#define MPU_RASR_ATTR_AP_RW_NA (1U << 24U) +#define MPU_RASR_ATTR_AP_RW_RO (2U << 24U) +#define MPU_RASR_ATTR_AP_RW_RW (3U << 24U) +#define MPU_RASR_ATTR_AP_RO_NA (5U << 24U) +#define MPU_RASR_ATTR_AP_RO_RO (6U << 24U) +#define MPU_RASR_ATTR_XN (1U << 28U) +/** @} */ + +/** + * @name Region attributes + * @{ + */ +#define MPU_RASR_ATTR_STRONGLY_ORDERED (MPU_RASR_ATTR_TEX(0)) +#define MPU_RASR_ATTR_SHARED_DEVICE (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B) +#define MPU_RASR_ATTR_CACHEABLE_WT_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_CACHEABLE_WB_NWA (MPU_RASR_ATTR_TEX(0) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_CACHEABLE (MPU_RASR_ATTR_TEX(1)) +#define MPU_RASR_ATTR_CACHEABLE_WB_WA (MPU_RASR_ATTR_TEX(1) | MPU_RASR_ATTR_B | MPU_RASR_ATTR_C) +#define MPU_RASR_ATTR_NON_SHARED_DEVICE (MPU_RASR_ATTR_TEX(2)) +/** @} */ + +/** + * @name Region identifiers + * @{ + */ +#define MPU_REGION_0 0U +#define MPU_REGION_1 1U +#define MPU_REGION_2 2U +#define MPU_REGION_3 3U +#define MPU_REGION_4 4U +#define MPU_REGION_5 5U +#define MPU_REGION_6 6U +#define MPU_REGION_7 7U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Enables the MPU. + * @note MEMFAULENA is enabled in SCB_SHCSR. + * + * @param[in] ctrl MPU control modes as defined in @p MPU_CTRL register, + * the enable bit is enforced + * + * @api + */ +#define mpuEnable(ctrl) { \ + MPU->CTRL = ((uint32_t)ctrl) | MPU_CTRL_ENABLE; \ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; \ +} + +/** + * @brief Disables the MPU. + * @note MEMFAULENA is disabled in SCB_SHCSR. + * + * @api + */ +#define mpuDisable() { \ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; \ + MPU->CTRL = 0; \ +} + +/** + * @brief Configures an MPU region. + * + * @param[in] region the region number + * @param[in] address start address of the region, note, there are alignment + * constraints + * @param[in] attribs attributes mask as defined in @p MPU_RASR register + * + * @api + */ +#define mpuConfigureRegion(region, addr, attribs) { \ + MPU->RNR = ((uint32_t)region); \ + MPU->RBAR = ((uint32_t)addr); \ + MPU->RASR = ((uint32_t)attribs); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* MPU_H */ + +#endif /* MPUV7M_H */ + +/** @} */ -- cgit v1.2.3