From c5ca297584502252e592342fb7a7eb95c3072548 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Thu, 22 Oct 2015 13:26:05 +0000 Subject: DMA-related adjustments. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8379 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 15 +++++++- os/hal/ports/STM32/STM32F0xx/stm32_rcc.h | 28 ++++++++++++++ os/hal/ports/STM32/STM32L0xx/hal_lld.c | 55 +++++++++++++++++++++++++++ os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 45 ++++++++++++++++++++-- 4 files changed, 139 insertions(+), 4 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index 901d30d1d..97f93340d 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -56,12 +56,25 @@ #define STM32_DMA_CCR_RESET_VALUE 0x00000000U #if STM32_DMA_SUPPORTS_CSELR == TRUE + +#if defined(DMA1_CSELR) #define ADDR_DMA1_CSELR &DMA1_CSELR->CSELR +#else +#define ADDR_DMA1_CSELR &DMA1->CSELR +#endif + +#if defined(DMA2_CSELR) #define ADDR_DMA2_CSELR &DMA2_CSELR->CSELR #else +#define ADDR_DMA2_CSELR &DMA2->CSELR +#endif + +#else /* !defined(DMA1_CSELR) */ + #define ADDR_DMA1_CSELR NULL #define ADDR_DMA2_CSELR NULL -#endif + +#endif /* !defined(DMA1_CSELR) */ /* * Default ISR collision masks. diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h index 6ecb97f1b..8fc8e933e 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h @@ -323,6 +323,34 @@ * @api */ #define rccResetDMA1() + +/** + * @brief Enables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA2() /** @} */ /** diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c index 70865b9de..5972a339e 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c @@ -85,6 +85,61 @@ static void hal_lld_backup_domain_init(void) { /* Driver interrupt handlers. */ /*===========================================================================*/ +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) +#if defined(STM32_DMA1_CH23_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 streams 2 and 3 shared ISR. + * @note It is declared here because this device has a non-standard + * DMA shared IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH23_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Check on channel 2.*/ + dmaServeInterrupt(DMA1, 2); + + /* Check on channel 3.*/ + dmaServeInterrupt(DMA1, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* defined(STM32_DMA1_CH23_HANDLER) */ + +#if defined(STM32_DMA1_CH4567_HANDLER) || defined(__DOXYGEN__) +/** + * @brief DMA1 streams 4, 5, 6 and 7 shared ISR. + * + * @isr + */ +OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + dmaServeInterrupt(DMA1, 4); + + /* Check on channel 5.*/ + dmaServeInterrupt(DMA1, 5); + +#if STM32_DMA1_NUM_CHANNELS > 5 + /* Check on channel 6.*/ + dmaServeInterrupt(DMA1, 6); +#endif + +#if STM32_DMA1_NUM_CHANNELS > 6 + /* Check on channel 7.*/ + dmaServeInterrupt(DMA1, 7); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif /* defined(STM32_DMA1_CH4567_HANDLER) */ +#endif /* defined(STM32_DMA_REQUIRED) */ + + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 05b61b39c..260f91917 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -68,6 +68,7 @@ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 #define STM32_DMA1_CH4567_HANDLER Vector6C @@ -75,7 +76,19 @@ #define STM32_DMA1_CH23_NUMBER 10 #define STM32_DMA1_CH4567_NUMBER 11 -#define STM32_DMA2_NUM_CHANNELS 0 +#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER +#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER +#define DMA1_CH2_CMASK 0x00000006U +#define DMA1_CH3_CMASK 0x00000006U + +#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER +#define DMA1_CH4_CMASK 0x00000078U +#define DMA1_CH5_CMASK 0x00000078U +#define DMA1_CH6_CMASK 0x00000078U +#define DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -296,6 +309,7 @@ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 #define STM32_DMA1_CH4567_HANDLER Vector6C @@ -303,7 +317,19 @@ #define STM32_DMA1_CH23_NUMBER 10 #define STM32_DMA1_CH4567_NUMBER 11 -#define STM32_DMA2_NUM_CHANNELS 0 +#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER +#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER +#define DMA1_CH2_CMASK 0x00000006U +#define DMA1_CH3_CMASK 0x00000006U + +#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER +#define DMA1_CH4_CMASK 0x00000078U +#define DMA1_CH5_CMASK 0x00000078U +#define DMA1_CH6_CMASK 0x00000078U +#define DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE @@ -531,6 +557,7 @@ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_CSELR TRUE #define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 #define STM32_DMA1_CH4567_HANDLER Vector6C @@ -538,7 +565,19 @@ #define STM32_DMA1_CH23_NUMBER 10 #define STM32_DMA1_CH4567_NUMBER 11 -#define STM32_DMA2_NUM_CHANNELS 0 +#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER +#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER +#define DMA1_CH2_CMASK 0x00000006U +#define DMA1_CH3_CMASK 0x00000006U + +#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER +#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER +#define DMA1_CH4_CMASK 0x00000078U +#define DMA1_CH5_CMASK 0x00000078U +#define DMA1_CH6_CMASK 0x00000078U +#define DMA1_CH7_CMASK 0x00000078U /* ETH attributes.*/ #define STM32_HAS_ETH FALSE -- cgit v1.2.3