From c5495d7351c6901d4bb9a34429f87d426f28577c Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 26 Dec 2017 09:45:33 +0000 Subject: Various RCC changes, ST driver working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11187 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c | 8 + os/hal/ports/STM32/STM32H7xx/stm32_rcc.h | 455 ++++++------------------------ 2 files changed, 100 insertions(+), 363 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c index fb0cccdac..292a16837 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c @@ -57,6 +57,8 @@ #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM2_STOP #elif defined(STM32L4XX) #define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP +#elif defined(STM32H7XX) +#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2 #else #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP #endif @@ -80,6 +82,8 @@ #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM3_STOP #elif defined(STM32L4XX) #define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP +#elif defined(STM32H7XX) +#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3 #else #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP #endif @@ -103,6 +107,8 @@ #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP #elif defined(STM32L4XX) #define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP +#elif defined(STM32H7XX) +#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM4 #else #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP #endif @@ -126,6 +132,8 @@ #define ST_ENABLE_STOP() DBGMCU->CR |= DBGMCU_CR_DBG_TIM5_STOP #elif defined(STM32L4XX) #define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP +#elif defined(STM32H7XX) +#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5 #else #define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP #endif diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h index a98525a97..70eb38cda 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h @@ -409,11 +409,9 @@ /** * @brief Disables the ADC1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) +#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN) /** * @brief Resets the ADC1 peripheral. @@ -434,11 +432,9 @@ /** * @brief Disables the ADC2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) +#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN) /** * @brief Resets the ADC2 peripheral. @@ -459,11 +455,9 @@ /** * @brief Disables the ADC3 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) +#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN) /** * @brief Resets the ADC3 peripheral. @@ -484,23 +478,21 @@ * * @api */ -#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp) +#define rccEnableDAC1(lp) rccEnableAPB1L(RCC_APB1LENR_DACEN, lp) /** * @brief Disables the DAC1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp) +#define rccDisableDAC1() rccDisableAPB1L(RCC_APB1LENR_DACEN) /** * @brief Resets the DAC1 peripheral. * * @api */ -#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST) +#define rccResetDAC1() rccResetAPB1L(RCC_APB1LRSTR_DACRST) /** @} */ /** @@ -519,11 +511,9 @@ /** * @brief Disables the DMA1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) +#define rccDisableDMA1() rccDisableAHB1(RCC_AHB1ENR_DMA1EN) /** * @brief Resets the DMA1 peripheral. @@ -544,11 +534,9 @@ /** * @brief Disables the DMA2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) +#define rccDisableDMA2() rccDisableAHB1(RCC_AHB1ENR_DMA2EN) /** * @brief Resets the DMA2 peripheral. @@ -627,116 +615,6 @@ #define rccDisableSRAM3() rccDisableAHB2(RCC_AHB2ENR_D2SRAM3EN) /** @} */ -/** - * @name PWR interface specific RCC operations - * @{ - */ -/** - * @brief Enables the PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Disables PWR interface clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) - -/** - * @brief Resets the PWR interface. - * - * @api - */ -#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) -/** @} */ - -/** - * @name CAN peripherals specific RCC operations - * @{ - */ -/** - * @brief Enables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Disables the CAN1 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) - -/** - * @brief Resets the CAN1 peripheral. - * - * @api - */ -#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) - -/** - * @brief Enables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Disables the CAN2 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) - -/** - * @brief Resets the CAN2 peripheral. - * - * @api - */ -#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) - -/** - * @brief Resets the CAN3 peripheral. - * - * @api - */ -#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST) - -/** - * @brief Enables the CAN3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp) - -/** - * @brief Disables the CAN3 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableCAN3(lp) rccDisableAPB1(RCC_APB1ENR_CAN3EN, lp) -/** @} */ - /** * @name ETH peripheral specific RCC operations * @{ @@ -755,13 +633,11 @@ /** * @brief Disables the ETH peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ - RCC_AHB1ENR_ETHMACTXEN | \ - RCC_AHB1ENR_ETHMACRXEN, lp) +#define rccDisableETH(...) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN) /** * @brief Resets the ETH peripheral. @@ -782,23 +658,21 @@ * * @api */ -#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) +#define rccEnableI2C1(lp) rccEnableAPB1L(RCC_APB1LENR_I2C1EN, lp) /** * @brief Disables the I2C1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) +#define rccDisableI2C1() rccDisableAPB1L(RCC_APB1LENR_I2C1EN) /** * @brief Resets the I2C1 peripheral. * * @api */ -#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) +#define rccResetI2C1() rccResetAPB1L(RCC_APB1LRSTR_I2C1RST) /** * @brief Enables the I2C2 peripheral clock. @@ -807,23 +681,21 @@ * * @api */ -#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) +#define rccEnableI2C2(lp) rccEnableAPB1L(RCC_APB1LENR_I2C2EN, lp) /** * @brief Disables the I2C2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) +#define rccDisableI2C2() rccDisableAPB1L(RCC_APB1LENR_I2C2EN) /** * @brief Resets the I2C2 peripheral. * * @api */ -#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +#define rccResetI2C2() rccResetAPB1L(RCC_APB1LRSTR_I2C2RST) /** * @brief Enables the I2C3 peripheral clock. @@ -832,23 +704,21 @@ * * @api */ -#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) +#define rccEnableI2C3(lp) rccEnableAPB1L(RCC_APB1LENR_I2C3EN, lp) /** * @brief Disables the I2C3 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) +#define rccDisableI2C3() rccDisableAPB1L(RCC_APB1LENR_I2C3EN) /** * @brief Resets the I2C3 peripheral. * * @api */ -#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) +#define rccResetI2C3() rccResetAPB1L(RCC_APB1LRSTR_I2C3RST) /** * @brief Enables the I2C4 peripheral clock. @@ -857,23 +727,21 @@ * * @api */ -#define rccEnableI2C4(lp) rccEnableAPB1(RCC_APB1ENR_I2C4EN, lp) +#define rccEnableI2C4(lp) rccEnableAPB1L(RCC_APB1LENR_I2C4EN, lp) /** * @brief Disables the I2C4 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_I2C4EN, lp) +#define rccDisableI2C4() rccDisableAPB1L(RCC_APB1LENR_I2C4EN) /** * @brief Resets the I2C4 peripheral. * * @api */ -#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_I2C4RST) +#define rccResetI2C4() rccResetAPB1L(RCC_APB1LRSTR_I2C4RST) /** @} */ /** @@ -892,11 +760,9 @@ /** * @brief Disables the OTG_FS peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp) +#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN) /** * @brief Resets the OTG_FS peripheral. @@ -917,11 +783,9 @@ /** * @brief Disables the OTG_HS peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp) +#define rccDisableOTG_HS() rccDisableAHB1(RCC_AHB1ENR_OTGHSEN) /** * @brief Resets the OTG_HS peripheral. @@ -942,11 +806,9 @@ /** * @brief Disables the OTG_HS peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) +#define rccDisableOTG_HSULPI() rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN) /** @} */ /** @@ -965,11 +827,9 @@ /** * @brief Disables the QUADSPI1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp) +#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN) /** * @brief Resets the QUADSPI1 peripheral. @@ -995,11 +855,9 @@ /** * @brief Disables the SDMMC1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSDMMC1(lp) rccDisableAPB2(RCC_APB2ENR_SDMMC1EN, lp) +#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN) /** * @brief Resets the SDMMC1 peripheral. @@ -1025,11 +883,9 @@ /** * @brief Disables the SPI1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) +#define rccDisableSPI1() rccDisableAPB2(RCC_APB2ENR_SPI1EN) /** * @brief Resets the SPI1 peripheral. @@ -1045,23 +901,21 @@ * * @api */ -#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) +#define rccEnableSPI2(lp) rccEnableAPB1L(RCC_APB1LENR_SPI2EN, lp) /** * @brief Disables the SPI2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) +#define rccDisableSPI2() rccDisableAPB1L(RCC_APB1LENR_SPI2EN) /** * @brief Resets the SPI2 peripheral. * * @api */ -#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +#define rccResetSPI2() rccResetAPB1L(RCC_APB1LRSTR_SPI2RST) /** * @brief Enables the SPI3 peripheral clock. @@ -1070,23 +924,21 @@ * * @api */ -#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) +#define rccEnableSPI3(lp) rccEnableAPB1L(RCC_APB1LENR_SPI3EN, lp) /** * @brief Disables the SPI3 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) +#define rccDisableSPI3() rccDisableAPB1L(RCC_APB1LENR_SPI3EN) /** * @brief Resets the SPI3 peripheral. * * @api */ -#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) +#define rccResetSPI3() rccResetAPB1L(RCC_APB1LRSTR_SPI3RST) /** * @brief Enables the SPI4 peripheral clock. @@ -1100,11 +952,9 @@ /** * @brief Disables the SPI4 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp) +#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN) /** * @brief Resets the SPI4 peripheral. @@ -1125,11 +975,9 @@ /** * @brief Disables the SPI5 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp) +#define rccDisableSPI5() rccDisableAPB2(RCC_APB2ENR_SPI5EN) /** * @brief Resets the SPI5 peripheral. @@ -1150,11 +998,9 @@ /** * @brief Disables the SPI6 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp) +#define rccDisableSPI6() rccDisableAPB2(RCC_APB2ENR_SPI6EN) /** * @brief Resets the SPI6 peripheral. @@ -1180,11 +1026,9 @@ /** * @brief Disables the TIM1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) +#define rccDisableTIM1(...) rccDisableAPB2(RCC_APB2ENR_TIM1EN) /** * @brief Resets the TIM1 peripheral. @@ -1200,23 +1044,21 @@ * * @api */ -#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) +#define rccEnableTIM2(lp) rccEnableAPB1L(RCC_APB1LENR_TIM2EN, lp) /** * @brief Disables the TIM2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) +#define rccDisableTIM2(...) rccDisableAPB1L(RCC_APB1LENR_TIM2EN) /** * @brief Resets the TIM2 peripheral. * * @api */ -#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) +#define rccResetTIM2() rccResetAPB1L(RCC_APB1LRSTR_TIM2RST) /** * @brief Enables the TIM3 peripheral clock. @@ -1225,23 +1067,21 @@ * * @api */ -#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) +#define rccEnableTIM3(lp) rccEnableAPB1L(RCC_APB1LENR_TIM3EN, lp) /** * @brief Disables the TIM3 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) +#define rccDisableTIM3(...) rccDisableAPB1L(RCC_APB1LENR_TIM3EN) /** * @brief Resets the TIM3 peripheral. * * @api */ -#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) +#define rccResetTIM3() rccResetAPB1L(RCC_APB1LRSTR_TIM3RST) /** * @brief Enables the TIM4 peripheral clock. @@ -1250,23 +1090,21 @@ * * @api */ -#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) +#define rccEnableTIM4(lp) rccEnableAPB1L(RCC_APB1LENR_TIM4EN, lp) /** * @brief Disables the TIM4 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) +#define rccDisableTIM4(...) rccDisableAPB1L(RCC_APB1LENR_TIM4EN) /** * @brief Resets the TIM4 peripheral. * * @api */ -#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) +#define rccResetTIM4() rccResetAPB1L(RCC_APB1LRSTR_TIM4RST) /** * @brief Enables the TIM5 peripheral clock. @@ -1275,7 +1113,7 @@ * * @api */ -#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) +#define rccEnableTIM5(lp) rccEnableAPB1L(RCC_APB1LENR_TIM5EN, lp) /** * @brief Disables the TIM5 peripheral clock. @@ -1284,14 +1122,14 @@ * * @api */ -#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) +#define rccDisableTIM5(lp) rccDisableAPB1L(RCC_APB1LENR_TIM5EN) /** * @brief Resets the TIM5 peripheral. * * @api */ -#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) +#define rccResetTIM5() rccResetAPB1L(RCC_APB1LRSTR_TIM5RST) /** * @brief Enables the TIM6 peripheral clock. @@ -1300,23 +1138,21 @@ * * @api */ -#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) +#define rccEnableTIM6(lp) rccEnableAPB1L(RCC_APB1LENR_TIM6EN, lp) /** * @brief Disables the TIM6 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) +#define rccDisableTIM6(...) rccDisableAPB1L(RCC_APB1LENR_TIM6EN) /** * @brief Resets the TIM6 peripheral. * * @api */ -#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) +#define rccResetTIM6() rccResetAPB1L(RCC_APB1LRSTR_TIM6RST) /** * @brief Enables the TIM7 peripheral clock. @@ -1325,23 +1161,21 @@ * * @api */ -#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) +#define rccEnableTIM7(lp) rccEnableAPB1L(RCC_APB1LENR_TIM7EN, lp) /** * @brief Disables the TIM7 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) +#define rccDisableTIM7(...) rccDisableAPB1L(RCC_APB1LENR_TIM7EN) /** * @brief Resets the TIM7 peripheral. * * @api */ -#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) +#define rccResetTIM7() rccResetAPB1L(RCC_APB1LRSTR_TIM7RST) /** * @brief Enables the TIM8 peripheral clock. @@ -1355,11 +1189,9 @@ /** * @brief Disables the TIM8 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) +#define rccDisableTIM8(...) rccDisableAPB2(RCC_APB2ENR_TIM8EN) /** * @brief Resets the TIM8 peripheral. @@ -1368,81 +1200,6 @@ */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) -/** - * @brief Enables the TIM9 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Disables the TIM9 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) - -/** - * @brief Resets the TIM9 peripheral. - * - * @api - */ -#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) - -/** - * @brief Enables the TIM10 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp) - -/** - * @brief Disables the TIM10 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp) - -/** - * @brief Resets the TIM10 peripheral. - * - * @api - */ -#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST) - -/** - * @brief Enables the TIM11 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Disables the TIM11 peripheral clock. - * - * @param[in] lp low power enable flag - * - * @api - */ -#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) - -/** - * @brief Resets the TIM11 peripheral. - * - * @api - */ -#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) - /** * @brief Enables the TIM12 peripheral clock. * @@ -1450,23 +1207,21 @@ * * @api */ -#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) +#define rccEnableTIM12(lp) rccEnableAPB1L(RCC_APB1LENR_TIM12EN, lp) /** * @brief Disables the TIM12 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) +#define rccDisableTIM12(...) rccDisableAPB1L(RCC_APB1LENR_TIM12EN) /** * @brief Resets the TIM12 peripheral. * * @api */ -#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) +#define rccResetTIM12() rccResetAPB1L(RCC_APB1LRSTR_TIM12RST) /** * @brief Enables the TIM13 peripheral clock. @@ -1475,23 +1230,21 @@ * * @api */ -#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) +#define rccEnableTIM13(lp) rccEnableAPB1L(RCC_APB1LENR_TIM13EN, lp) /** * @brief Disables the TIM13 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) +#define rccDisableTIM13(...) rccDisableAPB1L(RCC_APB1LENR_TIM13EN) /** * @brief Resets the TIM13 peripheral. * * @api */ -#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) +#define rccResetTIM13() rccResetAPB1L(RCC_APB1LRSTR_TIM13RST) /** * @brief Enables the TIM14 peripheral clock. @@ -1500,23 +1253,21 @@ * * @api */ -#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) +#define rccEnableTIM14(lp) rccEnableAPB1L(RCC_APB1LENR_TIM14EN, lp) /** * @brief Disables the TIM14 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) +#define rccDisableTIM14(...) rccDisableAPB1L(RCC_APB1LENR_TIM14EN) /** * @brief Resets the TIM14 peripheral. * * @api */ -#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) +#define rccResetTIM14() rccResetAPB1L(RCC_APB1LRSTR_TIM14RST) /** @} */ /** @@ -1535,11 +1286,9 @@ /** * @brief Disables the USART1 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) +#define rccDisableUSART1(...) rccDisableAPB2(RCC_APB2ENR_USART1EN) /** * @brief Resets the USART1 peripheral. @@ -1555,23 +1304,21 @@ * * @api */ -#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) +#define rccEnableUSART2(lp) rccEnableAPB1L(RCC_APB1LENR_USART2EN, lp) /** * @brief Disables the USART2 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) +#define rccDisableUSART2(...) rccDisableAPB1L(RCC_APB1LENR_USART2EN) /** * @brief Resets the USART2 peripheral. * * @api */ -#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) +#define rccResetUSART2() rccResetAPB1L(RCC_APB1LRSTR_USART2RST) /** * @brief Enables the USART3 peripheral clock. @@ -1580,23 +1327,21 @@ * * @api */ -#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) +#define rccEnableUSART3(lp) rccEnableAPB1L(RCC_APB1LENR_USART3EN, lp) /** * @brief Disables the USART3 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) +#define rccDisableUSART3(...) rccDisableAPB1L(RCC_APB1LENR_USART3EN) /** * @brief Resets the USART3 peripheral. * * @api */ -#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) +#define rccResetUSART3() rccResetAPB1L(RCC_APB1LRSTR_USART3RST) /** * @brief Enables the UART4 peripheral clock. @@ -1605,23 +1350,21 @@ * * @api */ -#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) +#define rccEnableUART4(lp) rccEnableAPB1L(RCC_APB1LENR_UART4EN, lp) /** * @brief Disables the UART4 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) +#define rccDisableUART4(...) rccDisableAPB1L(RCC_APB1LENR_UART4EN) /** * @brief Resets the UART4 peripheral. * * @api */ -#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) +#define rccResetUART4() rccResetAPB1L(RCC_APB1LRSTR_UART4RST) /** * @brief Enables the UART5 peripheral clock. @@ -1630,23 +1373,21 @@ * * @api */ -#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) +#define rccEnableUART5(lp) rccEnableAPB1L(RCC_APB1LENR_UART5EN, lp) /** * @brief Disables the UART5 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) +#define rccDisableUART5(...) rccDisableAPB1L(RCC_APB1LENR_UART5EN) /** * @brief Resets the UART5 peripheral. * * @api */ -#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) +#define rccResetUART5() rccResetAPB1L(RCC_APB1LRSTR_UART5RST) /** * @brief Enables the USART6 peripheral clock. @@ -1660,11 +1401,9 @@ /** * @brief Disables the USART6 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) +#define rccDisableUSART6(...) rccDisableAPB2(RCC_APB2ENR_USART6EN) /** * @brief Resets the USART6 peripheral. @@ -1680,23 +1419,21 @@ * * @api */ -#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp) +#define rccEnableUART7(lp) rccEnableAPB1L(RCC_APB1LENR_UART7EN, lp) /** * @brief Disables the UART7 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp) +#define rccDisableUART7(...) rccDisableAPB1L(RCC_APB1LENR_UART7EN) /** * @brief Resets the UART7 peripheral. * * @api */ -#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST) +#define rccResetUART7() rccResetAPB1L(RCC_APB1LRSTR_UART7RST) /** * @brief Enables the UART8 peripheral clock. @@ -1705,23 +1442,21 @@ * * @api */ -#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp) +#define rccEnableUART8(lp) rccEnableAPB1L(RCC_APB1LENR_UART8EN, lp) /** * @brief Disables the UART8 peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp) +#define rccDisableUART8(...) rccDisableAPB1L(RCC_APB1LENR_UART8EN) /** * @brief Resets the UART8 peripheral. * * @api */ -#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST) +#define rccResetUART8() rccResetAPB1L(RCC_APB1LRSTR_UART8RST) /** @} */ /** @@ -1739,12 +1474,10 @@ /** * @brief Disables the LTDC peripheral clock. - * - * @param[in] lp low power enable flag - * +. * * @api */ -#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp) +#define rccDisableLTDC() rccDisableAPB2(RCC_APB2ENR_LTDCEN) /** * @brief Resets the LTDC peripheral. @@ -1769,11 +1502,9 @@ /** * @brief Disables the DMA2D peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ -#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp) +#define rccDisableDMA2D() rccDisableAHB1(RCC_AHB1ENR_DMA2DEN) /** * @brief Resets the DMA2D peripheral. @@ -1803,14 +1534,12 @@ /** * @brief Disables the FSMC peripheral clock. * - * @param[in] lp low power enable flag - * * @api */ #if defined(STM32_FSMC_IS_FMC) - #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp) + #define rccDisableFSMC(...) rccDisableAHB3(RCC_AHB3ENR_FMCEN) #else - #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp) + #define rccDisableFSMC(...) rccDisableAHB3(RCC_AHB3ENR_FSMCEN) #endif /** -- cgit v1.2.3