From a4fa6c20411b4d5664ccf151f403a72d7e5bb4cc Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 12 May 2018 15:44:39 +0000
Subject: Fixed TIMPRE.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12029 110e8d01-0319-4d1e-a829-52ad28d1bb01
---
 os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h  | 61 +++++++++------------------
 os/hal/ports/STM32/STM32F4xx/stm32_registry.h |  2 +-
 2 files changed, 20 insertions(+), 43 deletions(-)

(limited to 'os/hal/ports')

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
index 253a832dc..e075816c8 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -2062,69 +2062,46 @@
 #define STM32_PLL48CLK              0
 #endif /* STM32_CLOCK48_REQUIRED */
 
-#if defined(STM32F446xx)
-#if STM32_TIMPRE == STM32_TIMPRE_HCLK
+#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) ||        \
+    defined(__DOXYGEN__)
 /**
  * @brief   Clock of timers connected to APB1
  *          (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
  */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \
-    (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \
-    (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_TIMCLK1               STM32_HCLK
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 4)
-#endif
-#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
 #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               STM32_HCLK
-#else /* !(STM32_TIMPRE_HCLK == STM32_TIMPRE_HCLK) */
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
 #define STM32_TIMCLK1               (STM32_PCLK1 * 2)
 #endif
-#endif /* STM32_TIMPRE == STM32_TIMPRE_HCLK */
 
-#if (STM32_TIMPRE == STM32_TIMPRE_HCLK) || defined(STM32F446xx)
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \
-    (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \
-    (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) ||            \
-    defined(__DOXYGEN__)
 /**
  * @brief   Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
  */
-#define STM32_TIMCLK2               STM32_HCLK
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 4)
-#endif
-#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
 #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               STM32_HCLK
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
 #else
 #define STM32_TIMCLK2               (STM32_PCLK2 * 2)
 #endif
-#endif /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
-
-#else /* !defined(STM32F446xx) */
 
-/**
- * @brief   Clock of timers connected to APB1
- *          (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \
+    (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \
+    (STM32_PPRE1 == STM32_PPRE1_DIV4) ||                                    \
+    defined(__DOXYGEN__)
+#define STM32_TIMCLK1               STM32_HCLK
 #else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 4)
 #endif
 
-/**
- * @brief   Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) ||                                    \
+    (STM32_PPRE2 == STM32_PPRE2_DIV2) ||                                    \
+    (STM32_PPRE2 == STM32_PPRE2_DIV4) ||                                    \
+    defined(__DOXYGEN__)
+#define STM32_TIMCLK2               STM32_HCLK
 #else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 4)
 #endif
-#endif /* !defined(STM32F446xx) */
+#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
 
 /**
  * @brief   Flash settings.
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index 3d6638de3..4c1d9b5e7 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -2868,7 +2868,7 @@
 /* Clock tree attributes.*/
 #define STM32_HAS_RCC_PLLSAI                FALSE
 #define STM32_HAS_RCC_PLLI2S                FALSE
-#define STM32_HAS_RCC_DCKCFGR               FALSE
+#define STM32_HAS_RCC_DCKCFGR               TRUE
 #define STM32_HAS_RCC_DCKCFGR2              FALSE
 #define STM32_HAS_RCC_I2SSRC                FALSE
 #define STM32_HAS_RCC_I2SPLLSRC             FALSE
-- 
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