From 745c0f1e34ce975eed8c74a4c3fb9b0f5ab3a108 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 13 May 2016 14:11:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9478 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c | 34 +- os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h | 457 ++++-------------------- os/hal/ports/STM32/STM32L4xx/platform.mk | 5 + os/hal/ports/STM32/STM32L4xx/stm32_rcc.h | 30 ++ os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 5 + 5 files changed, 123 insertions(+), 408 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c index 1b7eb5491..4f4036a15 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c @@ -30,17 +30,17 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define SPI1_RX_DMA_CHANNEL \ +#define QUADSPI1_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_QSPI_QUADSPI1_DMA_STREAM, \ - STM32_QUADSPI1_RX_DMA_CHN) + STM32_QUADSPI1_DMA_CHN) /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief SPI1 driver identifier.*/ +/** @brief QUADSPI1 driver identifier.*/ #if STM32_QSPI_USE_QUADSPI1 || defined(__DOXYGEN__) -SPIDriver QSPID1; +QSPIDriver QSPID1; #endif /*===========================================================================*/ @@ -59,13 +59,14 @@ SPIDriver QSPID1; */ static void qspi_lld_serve_dma_interrupt(QSPIDriver *qspip, uint32_t flags) { + (void)qspip; + (void)flags; + /* DMA errors handling.*/ #if defined(STM32_QSPI_DMA_ERROR_HOOK) if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { STM32_QSPI_DMA_ERROR_HOOK(qspip); } -#else - (void)flags; #endif } @@ -93,7 +94,7 @@ static void qspi_lld_serve_interrupt(QSPIDriver *qspip) { /*===========================================================================*/ /** - * @brief Low level SPI driver initialization. + * @brief Low level QSPI driver initialization. * * @notapi */ @@ -101,9 +102,9 @@ void qspi_lld_init(void) { #if STM32_QSPI_USE_QUADSPI1 qspiObjectInit(&QSPID1); - QSPID1.spi = SPI1; + QSPID1.qspi = QUADSPI; QSPID1.dma = STM32_DMA_STREAM(STM32_QSPI_QUADSPI1_DMA_STREAM); - QSPID1.dmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) | + QSPID1.dmamode = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_QSPI_QUADSPI1_DMA_PRIORITY) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | @@ -121,15 +122,15 @@ void qspi_lld_init(void) { * @notapi */ void qspi_lld_start(QSPIDriver *qspip) { - uint32_t ds; - /* If in stopped state then enables the SPI and DMA clocks.*/ + /* If in stopped state then enables the QUADSPI and DMA clocks.*/ if (qspip->state == QSPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == qspip) { +#if STM32_QSPI_USE_QUADSPI1 + if (&QSPID1 == qspip) { rccEnableQUADSPI1(FALSE); } #endif + } /* QSPI setup and enable.*/ // spip->spi->CR1 = 0; @@ -148,7 +149,7 @@ void qspi_lld_start(QSPIDriver *qspip) { */ void qspi_lld_stop(QSPIDriver *qspip) { - /* If in ready state then disables the SPI clock.*/ + /* If in ready state then disables the QUADSPI clock.*/ if (qspip->state == QSPI_READY) { /* QSPI disable.*/ @@ -157,8 +158,9 @@ void qspi_lld_stop(QSPIDriver *qspip) { dmaStreamRelease(qspip->dma); #if STM32_QSPI_USE_QUADSPI1 - if (&QSPID1 == qspip) + if (&QSPID1 == qspip) { rccDisableQUADSPI1(FALSE); + } #endif } } @@ -204,7 +206,7 @@ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp, dmaStreamSetTransactionSize(qspip->dma, n); dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M); - dmaStreamEnable(qspip->dmarx); + dmaStreamEnable(qspip->dma); } #endif /* HAL_USE_QSPI */ diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h index c3129a42f..14dc01b2f 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef HAL_SPI_LLD_H -#define HAL_SPI_LLD_H +#ifndef HAL_QSPI_LLD_H +#define HAL_QSPI_LLD_H #if HAL_USE_QSPI || defined(__DOXYGEN__) @@ -40,166 +40,33 @@ * @{ */ /** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. + * @brief QUADSPI1 driver enable switch. + * @details If set to @p TRUE the support for QUADSPI1 is included. * @note The default is @p FALSE. */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 FALSE +#if !defined(STM32_QSPI_USE_QUADSPI1) || defined(__DOXYGEN__) +#define STM32_QSPI_USE_QUADSPI1 FALSE #endif /** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 FALSE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI4 driver enable switch. - * @details If set to @p TRUE the support for SPI4 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI4 FALSE -#endif - -/** - * @brief SPI5 driver enable switch. - * @details If set to @p TRUE the support for SPI5 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI5 FALSE -#endif - -/** - * @brief SPI6 driver enable switch. - * @details If set to @p TRUE the support for SPI6 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI6 FALSE -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. + * @brief QUADSPI1 interrupt priority level setting. */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#if !defined(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QSPI_QUADSPI1_IRQ_PRIORITY 10 #endif /** - * @brief SPI3 interrupt priority level setting. + * @brief QUADSPI1 DMA priority (0..3|lowest..highest). */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#if !defined(STM32_QSPI_QUADSPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_QSPI_QUADSPI1_DMA_PRIORITY 1 #endif /** - * @brief SPI4 interrupt priority level setting. + * @brief QUADSPI DMA error hook. */ -#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI5 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI6 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI4_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI5 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI5_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI6 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI6_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI DMA error hook. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_QSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure") #endif /** @} */ @@ -207,188 +74,36 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4 -#error "SPI4 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5 -#error "SPI5 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6 -#error "SPI6 not present in the selected device" +#if STM32_QSPI_USE_QUADSPI1 && !STM32_HAS_QUADSPI1 +#error "QUADSPI1 not present in the selected device" #endif -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \ - !STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6 -#error "SPI driver activated but no SPI peripheral assigned" +#if !STM32_QSPI_USE_QUADSPI1 +#error "QSPI driver activated but no QUADSPI peripheral assigned" #endif -#if STM32_SPI_USE_SPI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI1" +#if STM32_QSPI_USE_QUADSPI1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to QUADSPI1" #endif -#if STM32_SPI_USE_SPI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SPI6" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI1" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI2" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI3" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI4" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI5" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY) -#error "Invalid DMA priority assigned to SPI6" +#if STM32_QSPI_USE_QUADSPI1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_QSPI_QUADSPI1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to QUADSPI1" #endif /* The following checks are only required when there is a DMA able to reassign streams to different channels.*/ #if STM32_ADVANCED_DMA /* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI1_TX_DMA_STREAM)) -#error "SPI1 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI2_TX_DMA_STREAM)) -#error "SPI2 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI3_TX_DMA_STREAM)) -#error "SPI3 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI4_TX_DMA_STREAM)) -#error "SPI4 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI5_TX_DMA_STREAM)) -#error "SPI5 DMA streams not defined" -#endif - -#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) || \ - !defined(STM32_SPI_SPI6_TX_DMA_STREAM)) -#error "SPI6 DMA streams not defined" +#if STM32_QSPI_USE_QUADSPI1 && !defined(STM32_QSPI_QUADSPI1_DMA_STREAM) +#error "QUADSPI1 DMA stream not defined" #endif /* Check on the validity of the assigned DMA channels.*/ -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 RX" -#endif - -#if STM32_SPI_USE_SPI1 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI1 TX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 RX" -#endif - -#if STM32_SPI_USE_SPI2 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI2 TX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 RX" -#endif - -#if STM32_SPI_USE_SPI3 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI3 TX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 RX" -#endif - -#if STM32_SPI_USE_SPI4 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI4 TX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 RX" -#endif - -#if STM32_SPI_USE_SPI5 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI5 TX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 RX" -#endif - -#if STM32_SPI_USE_SPI6 && \ - !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK) -#error "invalid DMA stream associated to SPI6 TX" +#if STM32_QSPI_USE_QUADSPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_QSPI_QUADSPI1_DMA_STREAM, STM32_QUADSPI1_DMA_MSK) +#error "invalid DMA stream associated to QUADSPI1" #endif #endif /* STM32_ADVANCED_DMA */ @@ -401,93 +116,69 @@ /*===========================================================================*/ /** - * @brief Type of a structure representing an SPI driver. + * @brief Type of a structure representing an QSPI driver. */ -typedef struct SPIDriver SPIDriver; +typedef struct QSPIDriver QSPIDriver; /** - * @brief SPI notification callback type. + * @brief Type of a QSPI notification callback. * - * @param[in] spip pointer to the @p SPIDriver object triggering the + * @param[in] qspip pointer to the @p QSPIDriver object triggering the * callback */ -typedef void (*spicallback_t)(SPIDriver *spip); +typedef void (*qspicallback_t)(QSPIDriver *qspip); /** * @brief Driver configuration structure. */ typedef struct { /** - * @brief Operation complete callback or @p NULL. + * @brief Operation complete callback or @p NULL. */ - spicallback_t end_cb; + qspicallback_t end_cb; /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI CR1 register initialization data. - */ - uint16_t cr1; - /** - * @brief SPI CR2 register initialization data. - */ - uint16_t cr2; -} SPIConfig; +} QSPIConfig; /** - * @brief Structure representing an SPI driver. + * @brief Structure representing an QSPI driver. */ -struct SPIDriver { +struct QSPIDriver { /** - * @brief Driver state. + * @brief Driver state. */ - spistate_t state; + qspistate_t state; /** - * @brief Current configuration data. + * @brief Current configuration data. */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) + const QSPIConfig *config; +#if QSPI_USE_WAIT || defined(__DOXYGEN__) /** * @brief Waiting thread. */ thread_reference_t thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#endif /* QSPI_USE_WAIT */ +#if QSPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) /** * @brief Mutex protecting the peripheral. */ mutex_t mutex; -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS +#endif /* QSPI_USE_MUTUAL_EXCLUSION */ +#if defined(QSPI_DRIVER_EXT_FIELDS) + QSPI_DRIVER_EXT_FIELDS #endif /* End of the mandatory fields.*/ /** - * @brief Pointer to the SPIx registers block. + * @brief Pointer to the QUADSPIx registers block. */ - SPI_TypeDef *spi; + QUADSPI_TypeDef *qspi; /** - * @brief Receive DMA stream. + * @brief QUADSPI DMA stream. */ - const stm32_dma_stream_t *dmarx; + const stm32_dma_stream_t *dma; /** - * @brief Transmit DMA stream. + * @brief QUADSPI DMA mode bit mask. */ - const stm32_dma_stream_t *dmatx; - /** - * @brief RX DMA mode bit mask. - */ - uint32_t rxdmamode; - /** - * @brief TX DMA mode bit mask. - */ - uint32_t txdmamode; + uint32_t dmamode; }; /*===========================================================================*/ @@ -498,44 +189,26 @@ struct SPIDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__) -extern SPIDriver SPID5; -#endif - -#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__) -extern SPIDriver SPID6; +#if STM32_QSPI_USE_QUADSPI1 && !defined(__DOXYGEN__) +extern QSPIDriver QSPID1; #endif #ifdef __cplusplus extern "C" { #endif void qspi_lld_init(void); - void qspi_lld_start(SPIDriver *spip); - void qspi_lld_stop(SPIDriver *spip); - void qspi_lld_send(SPIDriver *spip, size_t n, const uint8_t *txbuf); - void qspi_lld_receive(SPIDriver *spip, size_t n, uint8_t *rxbuf); + void qspi_lld_start(QSPIDriver *qspip); + void qspi_lld_stop(QSPIDriver *qspip); + void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp, + size_t n, const uint8_t *txbuf); + void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp, + size_t n, uint8_t *rxbuf); #ifdef __cplusplus } #endif #endif /* HAL_USE_QSPI */ -#endif /* HAL_SPI_LLD_H */ +#endif /* HAL_QSPI_LLD_H */ /** @} */ diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk index ee8210600..d81877000 100644 --- a/os/hal/ports/STM32/STM32L4xx/platform.mk +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -28,6 +28,9 @@ endif ifneq ($(findstring HAL_USE_USB TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c endif +ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +endif ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c endif @@ -67,6 +70,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/hal_i2c_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/hal_usb_lld.c \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c \ $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c \ @@ -90,6 +94,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1 \ + $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1 \ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \ diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index b991db746..83dfdffd1 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -554,6 +554,36 @@ #define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) /** @} */ +/** + * @name QUADSPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the QUADSPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp) + +/** + * @brief Disables the QUADSPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp) + +/** + * @brief Resets the QUADSPI1 peripheral. + * + * @api + */ +#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST) +/** @} */ + /** * @name SDMMC peripheral specific RCC operations * @{ diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 043259424..a1474a5c4 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -209,6 +209,11 @@ #define STM32_HAS_I2C4 FALSE +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_QUADSPI1_DMA_CHN 0x03000000 + /* RTC attributes.*/ #define STM32_HAS_RTC TRUE #define STM32_RTC_HAS_SUBSECONDS TRUE -- cgit v1.2.3