From 18e72e023de58ad2ca5757157eab5fa93ca0977a Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 16 Sep 2018 16:24:14 +0000 Subject: Adapted ADCv3 to STM32L4+. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12267 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | 50 +++++++++++++++++++++++------- os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h | 37 ++++++++++++++++++---- os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c | 4 +-- os/hal/ports/STM32/STM32L4xx+/platform.mk | 1 + 4 files changed, 73 insertions(+), 19 deletions(-) (limited to 'os/hal/ports') diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index c0bf010f5..4cba36650 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -121,7 +121,7 @@ static void adc_lld_vreg_on(ADCDriver *adcp) { osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10)); #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) adcp->adcm->CR = 0; /* RM 16.3.6.*/ adcp->adcm->CR = ADC_CR_ADVREGEN; #if STM32_ADC_DUAL_MODE @@ -147,7 +147,7 @@ static void adc_lld_vreg_off(ADCDriver *adcp) { #endif #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) adcp->adcm->CR = 0; /* RM 12.4.3.*/ adcp->adcm->CR = ADC_CR_DEEPPWD; #if STM32_ADC_DUAL_MODE @@ -175,7 +175,7 @@ static void adc_lld_analog_on(ADCDriver *adcp) { #endif #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) adcp->adcm->CR |= ADC_CR_ADEN; while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0) ; @@ -224,7 +224,7 @@ static void adc_lld_calibrate(ADCDriver *adcp) { #endif #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state"); adcp->adcm->CR |= ADC_CR_ADCAL; while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0) @@ -457,7 +457,11 @@ void adc_lld_init(void) { #if STM32_ADC_DUAL_MODE ADCD1.adcs = ADC2; #endif +#if STM32_DMA_SUPPORTS_DMAMUX + ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_CHANNEL); +#else ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM); +#endif ADCD1.dmamode = ADC_DMA_SIZE | STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | @@ -474,7 +478,11 @@ void adc_lld_init(void) { ADCD2.adcc = ADC123_COMMON; #endif ADCD2.adcm = ADC2; +#if STM32_DMA_SUPPORTS_DMAMUX + ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_CHANNEL); +#else ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM); +#endif ADCD2.dmamode = ADC_DMA_SIZE | STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | @@ -496,7 +504,11 @@ void adc_lld_init(void) { #if STM32_ADC_DUAL_MODE ADCD3.adcs = ADC4; #endif +#if STM32_DMA_SUPPORTS_DMAMUX + ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_CHANNEL); +#else ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM); +#endif ADCD3.dmamode = ADC_DMA_SIZE | STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | @@ -509,7 +521,11 @@ void adc_lld_init(void) { adcObjectInit(&ADCD4); ADCD4.adcc = ADC3_4_COMMON; ADCD4.adcm = ADC4; +#if STM32_DMA_SUPPORTS_DMAMUX + ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_CHANNEL); +#else ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM); +#endif ADCD4.dmamode = ADC_DMA_SIZE | STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) | STM32_DMA_CR_DIR_P2M | @@ -556,7 +572,7 @@ void adc_lld_init(void) { #endif #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); rccResetADC123(); #if defined(ADC1_2_COMMON) @@ -600,8 +616,11 @@ void adc_lld_start(ADCDriver *adcp) { #if defined(STM32F3XX) rccEnableADC12(true); #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); +#endif +#if STM32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC1); #endif } #endif /* STM32_ADC_USE_ADC1 */ @@ -619,8 +638,11 @@ void adc_lld_start(ADCDriver *adcp) { #if defined(STM32F3XX) rccEnableADC12(true); #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); +#endif +#if STM32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC2); #endif } #endif /* STM32_ADC_USE_ADC2 */ @@ -638,8 +660,11 @@ void adc_lld_start(ADCDriver *adcp) { #if defined(STM32F3XX) rccEnableADC34(true); #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); +#endif +#if STM32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC3); #endif } #endif /* STM32_ADC_USE_ADC3 */ @@ -657,8 +682,11 @@ void adc_lld_start(ADCDriver *adcp) { #if defined(STM32F3XX) rccEnableADC34(true); #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); +#endif +#if STM32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC4); #endif } #endif /* STM32_ADC_USE_ADC4 */ @@ -709,7 +737,7 @@ void adc_lld_stop(ADCDriver *adcp) { adc_lld_analog_off(adcp); adc_lld_vreg_off(adcp); -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; #endif @@ -768,7 +796,7 @@ void adc_lld_stop(ADCDriver *adcp) { #endif #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) if ((clkmask & 0x7) == 0) { rccDisableADC123(); } diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h index c274fa96d..27f3c6ff0 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h @@ -60,7 +60,7 @@ * @name Sampling rates * @{ */ -#if defined(STM32F3XX) +#if defined(STM32F3XX) || defined(__DOXYGEN__) #define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */ #define ADC_SMPR_SMP_2P5 1 /**< @brief 15 cycles conversion time. */ #define ADC_SMPR_SMP_4P5 2 /**< @brief 17 cycles conversion time. */ @@ -70,7 +70,7 @@ #define ADC_SMPR_SMP_181P5 6 /**< @brief 194 cycles conversion time. */ #define ADC_SMPR_SMP_601P5 7 /**< @brief 614 cycles conversion time. */ #endif -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) #define ADC_SMPR_SMP_2P5 0 /**< @brief 15 cycles conversion time */ #define ADC_SMPR_SMP_6P5 1 /**< @brief 19 cycles conversion time. */ #define ADC_SMPR_SMP_12P5 2 /**< @brief 25 cycles conversion time. */ @@ -319,14 +319,14 @@ #endif #endif /* defined(STM32F3XX) */ -#if defined(STM32L4XX) || defined(__DOXYGEN__) +#if defined(STM32L4XX) || defined(STM32L4XXP) || defined(__DOXYGEN__) /** * @brief ADC1/ADC2/ADC3 clock source and mode. */ #if !defined(STM32_ADC_ADC123_CLOCK_MODE) || defined(__DOXYGEN__) #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 #endif -#endif /* defined(STM32L4XX) */ +#endif /* defined(STM32L4XX) || defined(STM32L4XXP) */ /** @} */ @@ -365,6 +365,7 @@ #error "STM32_ADCx_NUMBER not defined in registry" #endif +#if !STM32_DMA_SUPPORTS_DMAMUX #if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_DMA_MSK)) || \ (STM32_ADC_USE_ADC2 && !defined(STM32_ADC2_DMA_MSK)) || \ (STM32_ADC_USE_ADC3 && !defined(STM32_ADC3_DMA_MSK)) || \ @@ -378,6 +379,7 @@ (STM32_ADC_USE_ADC4 && !defined(STM32_ADC4_DMA_CHN)) #error "STM32_ADCx_DMA_CHN not defined in registry" #endif +#endif /* !STM32_DMA_SUPPORTS_DMAMUX */ /* Units checks.*/ #if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 @@ -490,6 +492,27 @@ #endif /* Check on the presence of the DMA streams settings in mcuconf.h.*/ +#if STM32_DMA_SUPPORTS_DMAMUX + + +#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_CHANNEL) +#error "ADC1 DMA channel not defined" +#endif + +#if STM32_ADC_USE_ADC2 && !defined(STM32_ADC_ADC2_DMA_CHANNEL) +#error "ADC2 DMA channel not defined" +#endif + +#if STM32_ADC_USE_ADC3 && !defined(STM32_ADC_ADC3_DMA_CHANNEL) +#error "ADC3 DMA channel not defined" +#endif + +#if STM32_ADC_USE_ADC4 && !defined(STM32_ADC_ADC4_DMA_CHANNEL) +#error "ADC4 DMA channel not defined" +#endif + +#else /* !STM32_DMA_SUPPORTS_DMAMUX */ + #if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_STREAM) #error "ADC1 DMA stream not defined" #endif @@ -527,6 +550,8 @@ #error "invalid DMA stream associated to ADC4" #endif +#endif /* !STM32_DMA_SUPPORTS_DMAMUX */ + /* ADC clock source checks.*/ #if defined(STM32F3XX) #if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK @@ -562,7 +587,7 @@ #endif #endif /* defined(STM32F3XX) */ -#if defined(STM32L4XX) +#if defined(STM32L4XX) || defined(STM32L4XXP) #if STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK #define STM32_ADC123_CLOCK STM32_ADC12CLK #elif STM32_ADC_ADC123_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1 @@ -578,7 +603,7 @@ #if STM32_ADC123_CLOCK > STM32_ADCCLK_MAX #error "STM32_ADC123_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)" #endif -#endif /* defined(STM32L4XX) */ +#endif /* defined(STM32L4XX) || defined(STM32L4XXP) */ #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED diff --git a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c index ee42f18ab..dd718d385 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv2/hal_spi_lld.c @@ -223,8 +223,8 @@ void spi_lld_init(void) { spiObjectInit(&SPID2); SPID2.spi = SPI2; #if STM32_DMA_SUPPORTS_DMAMUX - SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL); - SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL); + SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL); + SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL); #else SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM); SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM); diff --git a/os/hal/ports/STM32/STM32L4xx+/platform.mk b/os/hal/ports/STM32/STM32L4xx+/platform.mk index 2d459eb47..38865ba9e 100644 --- a/os/hal/ports/STM32/STM32L4xx+/platform.mk +++ b/os/hal/ports/STM32/STM32L4xx+/platform.mk @@ -21,6 +21,7 @@ else endif # Drivers compatible with the platform. +include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk -- cgit v1.2.3